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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer description 1 ------table of contents------ overview the m16c/10 group (m30100 and M30102 groups) consist of single-chip microcomputers that use high- performance silicon gate cmos processes and have a on-chip m16c/60 series cpu core. the microcom- puters are housed in 32-pin plastic mold qfp or 48-pin plastic mold qfp packages. these single-chip microcomputers have both high function instructions and high instruction efficiency and feature a one- megabyte address space and the capability to execute instructions at high speed. the m30100 and M30102 groups consist of several products that have different on-chip memory types, sizes, and packages. features ? basic machine language instructions .. compatible with the m16c/60 series ? memory size ........................................rom/ram (see the memory expansion diagram.) ? shortest instruction execution time ...... 62.5 ns (when f(x in )=16mhz) ? power supply voltage ........................... 4.2 v to 5.5v (when f(x in )=16mhz) 2.7 v to 5.5v (when f(x in )=5mhz) (this is not applicable to applications for automobile use) ? interrupts .............................................. 12 internal causes, 7 external causes, 4 software causes (including key input interrupts) ? 8-bit timers ........................................... 4 with 8-bit prescaler (pwm output of timer y, z: selectable) ? 16-bit timer ........................................... 1 (time measurement timer) ? serial i/o .............................................. uart or clock synchronization type x 2 ? a-d converter ....................................... 10-bit x 12 channels (can be expanded to 14 channels) ? d-a converter ....................................... 1 ? watchdog timer .................................... 1 ? programmable i/o ports ...................... 34 ? led drive ports .................................... 8 ? clock generation circuits ...................... 3 internal circuits central processing unit (cpu) ..................... 10 reset ............................................................. 13 clock generation circuits ............................. 19 protection ...................................................... 34 overview of interrupts ................................... 35 watchdog timer ............................................ 57 timers ........................................................... 59 specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. ? main clock generation circuit an internal feedback resistor and an externally attached ceramic resonator/quartz crystal oscillator/rc oscillator. ? sub clock generation circuit an internal feedback resistor and an externally attached ceramic resonator/quartz crystal oscillator ? ring oscillator applications home appliances, office devices, audio, automobile, other serial i/o ....................................................... 97 a-d converter ............................................. 111 d-a conberter ............................................. 118 programmable i/o ports ............................. 120 precautionary note in using devices ......... 128 electric characteristics ............................... 133 flash memory version ................................ 146
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer description 2 12 34 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 29 28 27 26 25 32 31 30 x in x out v ss reset v cc cnv ss p1 7 /cntr 0 p3 7 /txd 1 /rxd 1 p0 3 /an 4 p0 2 /an 5 p0 1 /an 6 p0 0 /an 7 p0 6 /an 1 p0 5 /an 2 p0 4 /an 3 v ref p0 7 /an 0 p3 3 /tcin p3 0 /tx out p3 2 /ty out p3 1 /tz out ivcc v ss v cc m30100 (spvq p1 6 /clk 0 p1 5 /rxd 0 p1 4 /txd 0 p4 5 /int 0 p1 0 /ki 0 /an 8 p1 1 /ki 1 /an 9 p1 2 /ki 2 /an 1 0 p1 3 /ki 3 /an 11 pin configuration (top view) package: 32p6u-a figure 1.1.1. pin configuration diagram (top view) of the m30100 group pin configuration figures 1.1.1 and 1.1.2 show pin configurations (top view).
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer description 3 package: 48p6q-a pin configuration (top view) 12345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 36 35 34 33 45 44 43 42 41 48 47 46 40 39 38 37 M30102 (spvq x in x out v ss reset v cc cnv ss p4 6 /x cout p4 7 /x cin p1 7 /cntr 0 p3 6 /clk 1 p3 5 /rxd 1 p3 4 /clks 1 /da p0 3 /an 4 p0 2 /an 5 p0 1 /an 6 p0 0 /an 7 p3 7 /txd 1 /rxd 1 p0 6 /an 1 p0 5 /an 2 p0 4 /an 3 v ref n.c n.c n.c p0 7 /an 0 p4 1 /anex 1 p3 0 /tx out p4 0 /anex 0 p3 1 /tz out p3 2 /ty out ivcc p3 3 /tcin v ss v cc p4 2 /int 3 p4 3 /int 1 p1 6 /clk 0 p1 5 /rxd 0 p1 4 /txd 0 p2 1 n.c p2 0 p4 5 /int 0 p4 4 /int 2 p1 0 /ki 0 /an 8 p1 1 /ki 1 /an 9 p1 2 /ki 2 /an 10 p1 3 /ki 3 /an 11 figure 1.1.2. pin configuration diagram (top view) of the M30102 group
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer description 4 aaaaa aaaaa 8 8 5 1 r0l r0h r1h r1 l r 2 r 3 a 0 a 1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb sb isp usp intb flg pc timer timer 1 (8 bits) timer x (8 bits) timer y (8 bits) timer z (8 bits) timer c (16 bits) internal peripheral functions watchdog timer (15 bits) a-d converter (10 bits x 12 channels ) uart/clock synchronous si/o (8 bits x 1 channel) system clock generator xin-xout ring oscillation m16c/60 series 16-bit cpu core i/o ports port p0 port p1 port p3 port p4 registers stack pointers vector table multiplier memory rom (note 1) ram (note 2) program counter note 1: rom size depends on mcu type. note 2: ram size depends on mcu type. flag register uart (8 bits x 1 channel) figure 1.1.3. block diagram for the m30100 group block diagram figure 1.1.3 is a block diagram of the m30100 group.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer description 5 aaaaa aaaaa r0l r0h r1h r1 l r 2 r 3 a 0 a 1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb sb isp usp intb flg pc timer timer 1 (8 bits) timer x (8 bits) timer y (8 bits) timer z (8 bits) timer c (16 bits) internal peripheral functions watchdog timer (15 bits) a-d converter (10 bits x 12 channels, expandable to 14 channels) uart/clock synchronous si/o (8 bits x 2 channels) system clock generator x in -x out x cin -x cout ring oscillation m16c/60 series 16-bit cpu core i/o ports 8 port p0 8 port p1 2 port p2 8 port p4 registers stack pointers vector table multiplier memory rom (note 1) ram (note 2) program counter note 1: rom size depends on mcu type. note 2: ram size depends on mcu type. d-a converter (8 bits x 1 channel ) flag register 8 port p3 figure 1.1.4. block diagram for the M30102 group block diagram figure 1.1.4 is a block diagram of the M30102 group.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer description 6 table 1.1.1. m16c/10 group performance overview item performance m30100 M30102 number of basic instructions 91 instructions shortest instruction execution time 62.5 ns (when f(x in )=16mhz) memory rom see the memory expansion diagram. size ram see the memory expansion diagram. i/o port p0,p1,p3,p4: 22 lines p0 to p4: 34 lines multifunction t1 8 bits x 1 timer tx, ty, tz 8 bits x 3 tc 16 bits x 1 serial i/o (uart or clock synchronous) x 2 x 2 (one is exclusively for uart) a-d converter x 12 channels x 12 channels (maximum resolution: 10 bits) (expandable up to 14 channels) d-a converter 8 bits x 1 watchdog timer 15 bits x 1 (with prescaler) interrupts 12 internal causes, 7 external causes (4 for m30100), 4 software causes clock generating circuits 2 internal circuits 3 internal circuits power supply voltage 4.2 v to 5.5v (when f(x in )=16mhz) 2.7 v to 5.5v (when f(x in )=5mhz) (note) power consumption 100mw (vcc=5.0v, f(x in )=16mhz) 12mw (vcc=3.0v, f(x in )=5mhz) i/o i/o withstand voltage 5v characteristics output current 5ma (10ma:led drive port) device configuration cmos silicon gate package 32-pin lqfp 48-pin lqfp note: this voltage is not applicable to applications for automobile use. performance overview table 1.1.1 gives an overview of the m16c/10 group performance specification.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer description 7 1k ram (byte) 16k 24k rom ( m30100f3fp m30100f3tfp M30102f3fp M30102f3tfp m30100m3-xxxfp m30100m3t-xxxfp M30102m3-xxxfp M30102m3t-xxxfp 48k 2k aaaaaaa aaaaaaa aaaaaaa aaaaaaa m30100m2-xxxfp m30100m2t-xxxfp M30102m2-xxxfp M30102m2t-xxxfp 2.5k 32k aaaaaaa aaaaaaa aaaaaaa M30102m6-xxxfp M30102m6t-xxxfp 6oefs%fwfmpqnfou 1mboojoh4ubhf as of january, 2003 type no. m30 10 0 m 2 t - xxx fp package type: fp: package 32p6u, 48p6q rom no. omitted for flash memory version indicates differences in characteristics and usage etc: nothing: common t: automobiles memory type: m: mask rom version f: flash memory version m16c/10 group m16c family rom size: 2: 16 kbytes 3: 24 kbytes 6: 48 kbytes indicates pin count, etc (the value itself has no specific meaning) figure 1.1.5. memory expansion figure 1.1.6. type no., memory size, and package mitsubishi plans to release the following products in the m16c/10 group: (1) support for mask rom version and flash memory version (2) memory size (3) package 32p6u: plastic molded lqfp (mask rom version and flash memory version) 48p6q: plastic molded lqfp (mask rom version and flash memory version)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer pin description 8 v cc , v ss cnv ss x in x out v ref p0 0 to p0 7 p1 0 to p1 7 p3 0 to p3 7 p4 0 to p4 7 signal name power supply input cnv ss reset input clock input clock output reference voltage input i/o port p0 i/o port p1 i/o port p3 i/o port p4 supply 2.7 to 5.5 v to the v cc pin. supply 0 v to the v ss pin. function connect it to the v ss pin via resistance (about 5 k ? ). an l on this input resets the microcomputer. these pins are provided for the main clock oscillation circuit. connect a ceramic resonator or crystal between the x in and x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. this pin is a reference voltage input for the a-d converter. this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. these pins are shared with analog input pins. this is a 2-bit i/o port equivalent to p0. this is a 8-bit i/o port equivalent to p0. p4 0 to 4 1 are shared with analog inputs. p4 2 to p4 5 are shared with interrupt inputs. p4 6 to p4 7 are shared with the i/o pin of the clock oscillation circuit for the clock. pin name input input input output input input/output input/output i/o type input/output input/output reset p2 0 to p2 1 ivcc connect a capacitor (0.1 f) between this pin and v ss . i/o port p2 input/output this is an 8-bit i/o port equivalent to p0. p1 0 to p1 3 are shared with analog inputs and key input interrupts. p1 4 to p1 6 are shared with serial i/o pins. p1 7 is shared with timer input. can be used as an led drive port. this is a 8-bit i/o port equivalent to p0. p3 0 to p3 3 are shared with timer input/output. p3 4 to p3 7 are shared with serial i/o. p3 4 is shared with analog outputs. vcc, v ss pin description
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer memory 9 operation of functional blocks the m30100/M30102 contain the following devices on a single chip: rom and ram, which function as memory for storing instructions and data; a central processing unit (cpu) that executes operations; and peripheral devices, such as timers, serial i/o, an a-d converter, an d-a converter, and i/o ports. the individual devices are described below. memory figure 1.3.1 is a memory map. the address space extends the 1m bytes from address 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the m30100m2-xxxfp, there is 16k bytes of internal rom from fc000 16 to fffff 16 . the vector table for fixed interrupts such as the reset are mapped to fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the m30100m2-xxxfp, there is 1k byte of internal ram from 00400 16 to 007ff 16 . in addition to storing data, the ram also stores the stack used when calling subrou- tines and when interrupts are generated. the sfr area is mapped to 00000 16 to 000ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. figure 1.3.1. memory map 00000 16 xxxxx 16 fffff 16 00400 16 yyyyy 16 internal rom area sfr area (for details, see figures 1.6.1 and 1.6.2) internal ram area ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc xxxxx 16 m30100m2/m2t z M30102m2/m2t yyyyy 16 fc000 16 007ff 16 m30100m3/m3t/f3/f3t z M30102m3/m3t/f3/f3t M30102m6 /m6t internal ram area internal rom area memory size 007ff 16 00dff 16 fa000 16 f4000 16 1k byte 1k byte 2.5k byte 16k byte 24k byte 48k byte type no. memory size 6oefs%fwfmpqnfou 1mboojoh4ubhf
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer cpu 10 central processing unit (cpu) the cpu has a total of 13 registers shown in figure 1.4.1. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h, r1h), and low-order bits as (r0l, r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0, r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa aaaaaaa b15 b0 r3 (note) aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa aaaaaaa b15 b0 fb (note) aaaaaaa aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these registers consist of two register banks. aa aa aa aa aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa aa aa aa aa cdzsboiu ipl figure 1.4.1. central processing unit register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer cpu 11 (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 1.4.2 shows the flag register (flg). the following explains the function of each flag: ?bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ?bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ?bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ?bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0. ?bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ?bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow. ?bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer cpu 12 ?bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. _______ this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ?bits 8 to 11: reserved area ?bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ?bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) aa aa a a aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa cdzsboiu ipl b0b15 figure 1.4.2. flag register (flg)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer reset 13 figure 1.5.2. example reset circuit (example voltage check circuit) reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 200 sec. when the reset pin level is then returned to the h level, the reset status is cancelled and program execution resumes from the address in the reset vector table. since the value of ram is indeterminate when power is applied, the initial values must be set. also, if a reset signal is input during write to ram, the access to the ram will be interrupted. consequently, the value of the ram being written may change to an unintended value due to the interruption. figures 1.5.1 and 1.5.2 show the example reset circuit. figure 1.5.3 shows the reset sequence. figure 1.5.1. example reset circuit reset v cc example when v cc = 5v . 0.8v reset v cc 0v 0v 5v 5v 4.0v more than 200 sec bclk address bclk 28cycles ffffc 16 ffffe 16 content of reset vector internal ring oscillation reset more than 20 cycles are needed (internal clock) (internal address signal) example when v cc = 5v . v cc reset supply voltage detection circuit reset v cc 0v 0v 5v 5v 4.0v more than 200 sec figure 1.5.3. reset sequence
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer reset 14 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. (1) (0004 16 ) processor mode register 0 (2) (0005 16 ) processor mode register 1 (3) (0006 16 ) system clock control register 0 (4) (0007 16 ) system clock control register 1 (5) (6) (0009 16 ) address match interrupt enable register (7) (000a 16 ) (9) (11) (12) (13) (21) (20) (8) protect register (10) (14) (15) (16) (17) (18) (19) (36) (37) (38) (39) (40) (41) (42) (43) (44) (00a8 16 ) uart1 transmit/receive control register 0 (00ad 16 ) uart1 transmit/receive control register 1 (00b0 16 ) uart transmit/receive control register 2 (00a0 16 ) uart0 transmit/receive mode register (00a4 16 ) uart0 transmit/receive control register 0 (00a5 16 ) uart0 transmit/receive control register 1 01001000 00 0 00 0 0001 000 0 0 0 00 0 0001000 0 0010 0001000 0 0010 00 16 00 16 (00ac 16 ) uart1 transmit/receive mode register (51) (52) (49) (50) (48) (53) (54) (55) (56) (62) (60) (61) (58) (59) (57) (67) (66) (68) (69) (65) (00d4 16 ) a-d control register 2 (00d6 16 ) a-d control register 0 (00d7 16 ) a-d control register 1 (63) (64) (00e2 16 ) port p0 direction register (00e3 16 ) port p1 direction register (00e6 16 ) port p2 direction register (00e7 16 ) port p3 direction register (00ea 16 ) port p4 direction register (00fc 16 ) pull-up control register 0 (00fd 16 ) pull-up control register 1 (00fe 16 ) port p1 drive capacity control register frame base register (fb) address registers (a0/a1) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) data registers (r0/r1/r2/r3) 00000??? 00 16 00 16 00 16 00 16 0000 16 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 0 000 (46) (47) (45) uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register watchdog timer control register key input interrupt control register address match interrupt register 0 a-d conversion interrupt control register timer 1 interrupt control register timer x interrupt control register timer y interrupt control register timer z interrupt control register tcin interrupt control register timer c interrupt control register int3 interrupt control register int1 interrupt control register timer y secondary timer y primary timer y, z waveform output control register timer z secondary prescaler y int2 interrupt control register timer y, z mode register address match interrupt register 1 (000f 16 ) (0014 16 ) (0015 16 ) (0016 16 ) (004d 16 ) (0010 16 ) (0011 16 ) (0012 16 ) (004e 16 ) (0051 16 ) (0052 16 ) (0053 16 ) (0054 16 ) (0055 16 ) (0056 16 ) (0057 16 ) (0058 16 ) (005a 16 ) (005b 16 ) (005c 16 ) (005e 16 ) (0082 16 ) (0083 16 ) (0084 16 ) (0085 16 ) (0086 16 ) (0081 16 ) (005f 16 ) (0080 16 ) 000????? 0 ff 16 00 16 ff 16 ff 16 timer z primary (0087 16 ) ff 16 00 16 00 16 00 00 00 16 00 16 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 00 000 ? 00 00 oscillation stop detection register (000c 16 ) 0 00 0 1000 (001e 16 ) 0 int0 input filter select register int0 interrupt control register (005d 16 ) 00 000 ? 00 000 ? 0 00000 ff 16 ff 16 (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) prescaler z (71) (70) 00 00 16 00 16 (008a 16 ) timer y,z output control register (008b 16 ) timer x mode register 0 000 0 0 prescaler x timer x (008c 16 ) (008d 16 ) ff 16 ff 16 timer count source set register (008e 16 ) (0096 16 ) external input enable register (0098 16 ) key input enable register (009a 16 ) timer c control register 0 0 0000 0 0 clock prescaler reset flag (008f 16 ) 0 (009b 16 ) timer c control register 1 1 1 (72) 0 0 00 0 0000 0 0 cntr0 interrupt control register (0059 16 ) 000 ? 0 00 16 00 16 00 16 0 000000 (73) (00dc 16 ) d-a control register 0 0 00 figure 1.5.4. device's internal status after a reset is cleared
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer software wait 15 software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. figure 1.5.5 shows the processor mode register 0 and 1. software reset figure 1.5.5. processor mode register 0 and 1. processor mode register 0 (note) symbol address when reset pm0 0004 16 xxxx0x00 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 pm03 reserved bit software reset bit the device is reset when this bit is set to 1. the value of this bit is 0 when read. note: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. processor mode register 1 (note 1) symbol address when reset pm1 0005 16 00xxx0x0 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to this bits, write 0. the value, if read, turns out to be indeterminate. reserved bit must always be set to 0 0 note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: after setting this bit to "1", can not change to "0" by software. a aa a aa a aa must always be set to 0 pm12 wdt interrupt/reset switching bit 0 : watchdog timer interrupt 1 : reset (note 2) a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. 00 0 nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. 0 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. reserved bit must always be set to 0 a a a a
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer sfr 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) timer x interrupt control register (txic) uart0 transmit interrupt control register (s0tic) timer 1 interrupt control register (t1ic) timer y interrupt control register (tyic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) key input interrupt control register (kupic) a-d conversion interrupt control register (adic) int1 interrupt control register (int1ic) tcin interrupt control register (tcinic) timer z interrupt control register (tzic) int0 interrupt control register (int0ic) timer c interrupt control register (tcic) oscillation stop detection register (cm2) int0 input filter select register (int0f) int3 interrupt control register (int3ic) int2 interrupt control register (int2ic) cntr0 interrupt control register (cntr0ic) figure 1.6.1. location of peripheral unit control registers (1) note: the blank area is reserved and must not be read or written.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer sfr 17 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 0087 16 0088 16 0089 16 008a 16 008b 16 008c 16 008d 16 008e 16 008f 16 0090 16 0091 16 0092 16 0093 16 0094 16 0095 16 0096 16 0097 16 0098 16 0099 16 009a 16 009b 16 009c 16 009d 16 009e 16 009f 16 00a0 16 00a1 16 00a2 16 00a3 16 00a4 16 00a5 16 00a6 16 00a7 16 00a8 16 00a9 16 00aa 16 00ab 16 00ac 16 00ad 16 00ae 16 00af 16 00b0 16 00b1 16 00b2 16 00b3 16 00b4 16 00b5 16 00b6 16 00b7 16 00b8 16 00b9 16 00ba 16 00bb 16 00bc 16 00bd 16 00be 16 00bf 16 timer y, z mode register (tyzmr) timer y secondary (tysc) external input enable register (inten) key input enable register (kien) timer c control register 1 (tcc1) time measurement register (tm) timer y, z waveform output control register (pum) timer c control register 0 (tcc0) timer y primary (typr) prescaler y (prey) uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart transmit/receive control register 2 (ucon) timer z secondary (tzsc) timer z primary (tzpr) prescaler z (prez) timer x mode register (txmr) timer x (tx) timer count source set register (tcss) prescaler x (prex) timer y, z output control register (tyzoc) prescaler 1 (pre1) timer 1 (t1) timer c counter (tc) clock prescaler reset flag (cpsrf) 00c0 16 00c1 16 00c2 16 00c3 16 00c4 16 00c5 16 00c6 16 00c7 16 00c8 16 00c9 16 00ca 16 00cb 16 00cc 16 00cd 16 00ce 16 00cf 16 00d0 16 00d1 16 00d2 16 00d3 16 00d4 16 00d5 16 00d6 16 00d7 16 00d8 16 00d9 16 00da 16 00db 16 00dc 16 00dd 16 00de 16 00df 16 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 00e9 16 00ea 16 00eb 16 00ec 16 00ed 16 00ee 16 00ef 16 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 00f6 16 00f7 16 00f8 16 00f9 16 00fa 16 00fb 16 00fc 16 00fd 16 00fe 16 00ff 16 a-d register (ad) port p0 (p0) port p0 direction register (pd0) port p1 (p1) port p1 direction register (pd1) port p2 (p2) port p2 direction register (pd2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) pull-up control register 0 (pur0) pull-up control register 1 (pur1) port p1 drive capacity control register (drr) a-d control register 0 (adcon0) a-d control register 1 (adcon1) a-d control register 2 (adcon2) d-a register (da) d-a control register (dacon) figure 1.6.2. location of peripheral unit control registers (2) note: the blank area is reserved and must not be read or written.
bus control under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 18 bus control during access, the memory areas (rom, ram, flash, etc.) and the sfr area have different bus cycles. as shown in table 1.7.1, memory areas can be accessed in one cycle of the cpu operation clock bclk. the sfr area can be accessed in two cycles of bclk. the memory areas and the sfr area also have different bus widths. the memory areas have a 16-bit bus width, while the sfr area has an 8-bit bus width. consequently, different operations are used when the areas are accessed in word (16 bits) units. table 1.7.2 shows the bus cycles that are necessary to access the sfr area and the memory areas. area even address byte access bclk data bclk bclk bclk bclk bclk bclk bclk address sfr area memory area even odd data data data data word data data data data data data data odd odd odd+1 odd odd+1 even even even+1 even/even+1 data address data address data address data address data address data address data address add address byte access even address word access add address word access 00000 16 xxxxx 16 fffff 16 00400 16 yyyyy 16 internal rom area sfr area (for details, see figures 1.6.1 and 1. 6.2) internal ram area sfr area memory area table 1.7.1. bus cycles for access areas area bus cycle sfr 2 bclk cycles internal rom/ram 1 bclk cycles figure 1.7.1. sfr area and memory areas table 1.7.2. cycles for access areas
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 19 clock generating circuit the clock generating circuit contains three oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. example of oscillator circuit figure 1.8.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 1.8.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 1.8.1 and 1.8.2 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note : insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. microcomputer x in x out r c microcomputer (built-in feedback resistor) external ceramic oscillator external rc oscillator external clock input clock generating circuit table 1.8.1. main clock, sub-clock, and ring oscillator generating circuits main clock generating circuit sub clock generating circuit ring oscillator generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer 1/x/y/zs count ? internal peripheral units operating clock source clock source operating clock source ? timer ys count clock source usable oscillator (note) ceramic, crystal or rc crystal oscillator C oscillator pins to connect oscillator x in , x out x cin , x cout none (has internal pins) oscillation stop/restart function available available available oscillator status immediately oscillating stopped oscillating after reset other externally derived clock can be input C note : when not using the main clock generating circuit, pull up the x in pin and leave the x out pin open. also, set the main clock stop bit (bit 5 of address 0006) to "1" (stop). figure 1.8.1. examples of main clock
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 20 sub clock cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 cm2i : bit i at address 000c 16 wdci : bit i at address 000f 16 cm10 1 write signal wait instruction main clock interrupt request level judgment output reset software reset details of divider cm04 f c32 x cin 1/32 x cout qs r x out cm05 f c x in r qs 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a b 1/2 c main clock switching circuit ring oscillator oscillation circuit cm20 oscillation stop detection cm22 f 1 f c cm07 = 0 f ad a d f 8 f 32 cb bcl k cm07 = 1 r cm02 1/2 f ring divider f main microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. clock generating circuit a ring oscillator is built into the microcomputer. the oscillation of the ring oscillator can be used as the bclk by setting the main clock select bit (bit 2 of address 000c). lower power consumption can be realized because the oscillating frequency of the ring oscillator is much lower compared to that of x in . the frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies and obtain the sufficient margin when designing application products. clock control figure 1.8.3 shows the block diagram of the clock generating circuit. figure 1.8.2. examples of sub-clock figure 1.8.3. clock generating circuit
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 21 clock generating circuit the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after reset, oscillation starts. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the x out pin can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the x out pin reduces the power dissipation. this bit changes to 1 when shifting from high- speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissi- pation mode to stop mode, the value before stop mode is retained. (2) sub-clock the sub-clock is generated by the sub-clock oscillation circuit. no sub-clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub-clock can be selected as bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub-clock oscillation has fully stabilized before switching. after the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the x cout pin can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the x cout pin reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu. the clock source for bclk is as follows: (1) the clock derived by dividing the main clock by 1, 2, 4, 8, or 16, (2) f c , or (3) the clock derived by dividing the clock supplied by the ring oscillator circuit (f ring ) by 1, 2, 4, 8 or 16. after reset, the bclk is derived by dividing the f ring by 8. when using an external rc oscillator circuit for the main clock, 1 division of the main clock cannot be selected as bclk. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high- speed/medium-speed mode to stop mode and at reset. when shifting from low-speed/low power dissipa- tion mode to stop mode, the value before stop mode is retained. (4) peripheral function clock a. f 1 , f 8 , f 32 the clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. the peripheral function clock is stopped as follows: (i) by stopping the main clock or (ii) by executing an wait instruction after setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1. when using an external rc oscillator circuit for the main clock, f 1 cannot be selected as the operation clock of some peripheral devices. b. f ad this clock has the same frequency as the main clock and is used in a-d conversion. (5) f c32 this clock is derived by dividing the sub-clock by 32. it is used for the timer 1, timer x, timer y and timer z counts. figure 1.8.6 shows the block diagram of fc 32 . (6) f c this clock has the same frequency as the sub-clock. it is used for bclk and for the watchdog timer. (7) f ring this clock is supplied by the ring oscillator circuit. in the ring oscillator mode, the clock divided by the division ratio selected with the main clock division select bit 0 and bit 1(bit 6 at address 0006 16 , and bit 6 and bit 7 at address 0007 16 ) is supplied as bclk. immediately after reset, 8 divisions of this clock is supplied as bclk. the ring oscillator oscillation can be set to bclk when oscillation stop is detected or with the main clock switching bit (bit 2 at address 000c 16 ).
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 22 system clock control register 0 (note 1) symbol address when reset cm0 0 006 16 48 16 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm07 cm05 cm04 cm03 cm02 cm06 reserved bit wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 3,4,5) 0 : on 1 : off main clock division select bit 0 (note 7) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: changes to 1 when shifting to stop mode. note 3: this bit is used to stop the main clock when placing the device in a low-power mode. if you want to operate with x in after exiting from the stop mode, set this bit to 0. when operating with a self-excited oscillator, set the system clock select bit (cm07) to 1 before setting this bit to 1. note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to 1, x out turns h. the built-in feedback resistor remains being on, so x in turns pulled up to x out (h) via the feedback resistor. note 6: set port xc select bit (cm04) to 1 before setting this bit to 1. can not write to both bits at the same time. note 7: this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 8: fc 32 is not included. do not set to 1 when using low-speed, low power dissipation or ring oscillator mode. system clock control register 1 (note 1) symbol address when reset cm1 0 007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note 4) 0 : clock on 1 : all clocks off (stop mode) cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high wr wr cm16 cm17 reserved bit always set to 0 ring oscillation stop bit 0 : oscillation enabled 1 : oscillation stopped (note 5) main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 reserved bit 0 : ceramic oscillation or crystal oscillation 1 : rc oscillation x in oscillation select bit always set to 0 0 a aa a aa a aa a aa a aa a aa a aa a aa a aa a a aa aa a a aa aa a a aa aa a aa a aa note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: this bit changes to 1 when shifting from high-speed/middle-speed mode to stop mode or at reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is 0. if 1, division mode is fixed at 8. note 4: if this bit is set to 1, x out turns h, and the built-in feedback resistor is ineffective. the mode of power control cannot be shifted to the stop mode directly from the oscillator mode. note 5: this bit can be set to 1 only when both the main clock switch bit (cm22) and clock monitor bit (cm23) are set to 0 . moreover, this bit is automatically set to 0 if the main clock switch bit (cm22) is set to 1. always set to 0 00 cm13 cm14 clock generating circuit figure 1.8.4. system clock control registers 0 and 1
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 23 symbol address when reset cpsrf 008f 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0) cpsr wr nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. a aa clock generating circuit b7 b6 b5 b4 b3 b2 b1 b0 rw cm20 cm21 cm22 cm23 0 00 0 oscillation stop detection register (note 5) symbol a ddress when reset cm2 000c 16 04 16 bit name function bit symbol main clock switch bit oscillation stop detection interrupt enable bit 0: the function is invalid. 1: the function is valid. 0: select x in clock. 1: select ring oscillator. 0: disabled 1: enabled 0: x in oscillating normally 1: x in stopping abnormally oscillation stop detection bit clock monitor bit reserved bit always set to "0" note 1: set to 0 before stopping the oscillation of the main clock (x in -x out ). (stop mode, low power dissipation mode, ring oscillation mode) an oscillation stop is detected if the oscillation of the main clock (x in -x out ) is stopped when the following two conditions are satisfied: (1) the oscillation stop detection function is valid and (2) cm21=1. note 2: valid when cm20=1. note 3: cm22 bit switches to 1 automatically if an oscillation stop is detected when both cm20 bit and cm 21 bit are 1. cm22 bit cannot be cleared when cm23=1. note 4: this bit is valid when cm20 bit is 1. use this bit for the purpose of confirming x in operation for oscillation stop detection interrupt execution. note 5: in case of writing to this register, set bit 0 of the protect register(000a 16 ) to "1". (note 3) (note 2) (note 1) (note 4) figure 1.8.5. oscillation stop detection register and clock prescaler reset flag 1/32 f c32 x cin clock prescaler reset flag (bit 7 at address 008f 16 ) set to 1 reset clock prescaler figure 1.8.6. fc 32 block diagram
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 24 stop mode, wait mode pin states port retains status before stop mode stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc re- mains above 2v. because the oscillation of bclk, f 1 to f 32 , fc, fc 32 , and f ad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer x operate provided that the event counter mode is set to an external pulse, and uart0 and uart1 function provided an external clock is selected. table 1.8.2 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0 before shifting to stop mode. if returning by an interrupt, that interrupt routine is executed. if only a hardware reset is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. when shifting from high-speed/medium-speed mode to stop mode or at a reset, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. the stop mode must not be used while operating in the ring oscillator mode. wait mode when a wait instruction is executed, bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 1.8.3 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts using as bclk, the clock that had been selected when the wait instruction was executed. pin states port retains status before wait mode table 1.8.2. port status during stop mode table 1.8.3. port status during wait mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 25 status transition of bclk status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 1.8.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. when reset, division by 8 mode is set. the main clock division select bit 0 (bit 6 at address 0006 16 ) changes to 1 when shifting from high-speed/medium-speed mode to stop mode or at a reset. the follow- ing shows the operational modes of bclk. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. when going to low-speed or lower power dissipation mode, sure the sub-clock is oscillating stably. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is divided by 1 to obtain the bclk. when using an external rc circuit for the main clock, no-division mode must not be used. (6) low-speed mode f c is used as bclk. note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub- clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. (8) ring oscillator mode this mode sets the ring oscillator as bclk. the same as when x in is the main clock, the modes are no division, 2-division, 4-division, 8-division, and 16-division. note: before the count source for bclk can be changed from x in to xc in or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow a wait time in software for the oscillation to stabilize before switching over the clock. and, be sure to shift from division by 8 mode when you change it to ring oscillator mode. shift to other mode after you surely shift to the mode for division by 8 mode when you change it from ring oscillator mode to other mode.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 26 table 1.8.4. operating modes dictated by settings of system clock control registers 0 and 1 0 0 1 0 0 0 invalid division by 2 mode 0 1 0 0 0 0 invalid division by 4 mode 0 invalid invalid 0 1 0 invalid division by 8 mode 0 1 1 0 0 0 invalid division by 16 mode 0 0 0 0 0 0 invalid no-division mode 0 invalid invalid 1 invalid 0 1 low-speed mode 0 invalid invalid 1 invalid 1 1 low power dissipation mode 1 0 1 0 0 invalid invalid ring oscillator mode(divided by 2) 1 1 0 0 0 invalid invalid ring oscillator mode(divided by 4) 1 invalid invalid 0 1 invalid invalid ring oscillator mode(divided by 8) 1 1 1 0 0 invalid invalid ring oscillator mode(divided by 16) 1 0 0 0 0 invalid invalid ring oscillator mode(no division) cm22 cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk
power control under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 27 power control this section gives an overview of power control. modes there are three power save modes. (1) normal operating mode ? high-speed mode in this mode, one main clock cycle forms bclk. the cpu operates on the bclk. the peripheral functions operate on the clocks specified for each respective function. ? medium-speed mode in this mode, the main clock is divided into 2, 4, 8, or 16 to form bclk. the cpu operates on the bclk. the peripheral functions operated on the clocks specified for each respective function. ? low-speed mode in this mode, fc forms bclk. the cpu operates on the fc clock. fc is the clock supplied by the subclock. the peripheral functions operate on the clocks specified for each respective function. ? low power-dissipation mode this mode is selected when the main clock is stopped from low-speed mode. the cpu operates on the fc clock. fc is the clock supplied by the subclock. only the peripheral functions for which the subclock was selected as the count source continue to run. ? ring oscillator mode this mode sets the ring oscillator as bclk. the ring oscillator can be set to no division, 2-divisions, 4- division, 8-division, or 16-division mode according to the settings for cm06, cm16, and cm17. in- creasing the division ratio lowers power consumption. when the microcomputer is operating with the ring oscillator, the x in clock driver can be stopped by setting the main clock stop bit to 1. this can lower the power dissipation even more. (2) wait mode cpu operation is halted in this mode. the oscillator continues to run. (3) stop mode all oscillators stop in this mode. the cpu and internal peripheral functions all stop. of all 3 power saving modes, power savings are greatest in this mode. the mode cannot be shifted to the stop mode directly from the ring oscillator mode. figure 1.9.1 and 1.9.2 show the transition between each of the three modes, (1), (2), and (3).
power control under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 28 figure 1.9.1. clock transition (1) transition of stop mode, wait mode reset medium-speed mode (divided-by-8 mode) interrupt cm10 = 1 all oscillators stopped c pu operation stopped high-speed/medium- speed mode low-speed/low power dissipation mode normal mode stop mode stop mode stop mode all oscillators stopped all oscillators stopped wait mode wait mode wait mode cpu operation stopped cpu operation stopped interrupt wait instruction interrupt wait instruction interrupt wait instruction cm10 = 1 interrupt interrupt cm10 = 1 (refer to fig. 1. 9. 2. for the transition of normal mode.) ring oscilltor mode (divided-by-8 mode) wait mode cpu operation stopped interrupt wait instruction
power control under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 29 cm07=?? (note 1) cm06=? cm04=? cm04=? (notes 1, 3) cm04=? bclk: f(x in )/8 cm07=?? cm06=? cm06=? bclk: f( ring )/8 cm07=? cm06=? cm22=? bclk: f( ring )/8 cm07=?? cm06=? cm05=? cm22=? bclk: f( ring )/2 bclk: f( ring ) cm07=?? cm06=? cm05=?? cm22=? cm16=?? cm17=? cm22=? cm22=?? (note 1) bclk: f( ring )/16 bclk: f( ring )/4 transition of normal mode main clock is oscillating sub clock is stopped medium-speed mode (divided-by-8 mode) low-speed mode high-speed mode main clock is oscillating sub clock is stopped main clock is stopped sub clock is oscillating main clock is oscillating sub clock is oscillating low power dissipation mode bclk : f(x in )/2 cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 1 medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 1 medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 0 medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 0 bclk : f(x in )/8 medium-speed mode (divided-by-8 mode) cm07 = 0 cm06 = 1 high-speed mode bclk : f(x in )/2 cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 1 medium-speed mod (divided-by-2 mode) bclk : f(x in )/16 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 1 medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 0 medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 0 bclk : f(x cin ) cm07 = 1 cm06 = 1 bclk : f(x cin ) cm07 = 1 cm06 = 1 main clock is oscillating sub clock is oscillating cm07 = 0 (notes 1, 3) cm07 = 1 cm06 = 1 (note 2,5) cm07 = 0 (note 1) cm06 = 0 (note 3) cm04 = 1 cm05 = 0 cm05 = 1 cm04 = 0 cm04 = 1 cm06 = 0 (notes 1,3) note 1: switch clock after oscillation of main clock is sufficiently stable. note 2: switch clock after oscillation of sub clock is sufficiently stable. note 3: change cm17 and cm16 before changing cm06. note 4: transit in accordance with arrow. note 5: before switching bclk to other from the main clock, divide the main clock by 8 for safty purposes to switch bclk to the main clock again. main clock is oscillating sub clock is stopped ring oscillator mode (divided-by-8 mode) main clock is stopped sub clock is stopped ring oscillator mode cm05 = 0 cm05 = 1 8-division mode 1-division mode (note 3) 2-division mode (note 3) 16-division mode (note 3) 4-division mode (note 3) cm07= 0 cm06= 0 cm05= 1 cm22= 1 cm16= 1 cm17= 0 cm07= 0 cm06= 0 cm05= 1 cm22= 1 cm16= 1 cm17= 1 cm07= 0 cm06= 0 cm05= 1 cm22= 1 cm16= 0 cm17= 1 figure 1.9.2. clock transition (2)
oscillation stop detection under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 30 oscillation stop detection function the oscillation stop detection function detects abnormal stopping of the main clock by causes such as opening and shorting of the x in oscillation circuit. when oscillation stop is detected, an oscillation stop detection interrupt is issued. when an oscillation stop detection interrupt is issued, the ring oscillator in the microcomputer operates automatically and is used as the main clock in place of the x in clock. this allows interrupt processing. the oscillation stop detection function can be enabled/disabled with bit 0 and bit 1 of the oscillation stop detection register. when this bit is set to 11 2 , the function is enabled. after the reset is released, the oscillation stop detection function becomes disabled because the bit value is 00 2 . table 1.10.1 gives an specification overview of the oscillation stop detection function, figure 1.10.2 is a configuration diagram of the oscillation stop detection circuit and figure 1.10.3 shows the configuration of the oscillation stop detection register. table 1.10.1. specification overview of the oscillation stop detection function item specification oscillation stop detectable clock and x in 2 mhz frequency bandwidth enabling condition for oscillation stop when the oscillation stop detection bit (bit 0 of address 000c 16 ) detection function and the oscillation stop detection interrupt enable bit (bit 1 of address 000c 16 ) are set to 1 operation at oscillation stop detection ? oscillation stop detection interrupt occurs notes on stop mode, low power before stopping the main clock (x in -x out ), set the dissipation mode, and ring oscillator oscillation stop detection enable bit to 0 to disable the mode oscillation stop detection function. enable main clock (x in -x out ) oscillation and after the oscillation stabilizes, set the bit to 1 again. notes on wait mode if the peripheral function clock is stopped in wait mode with the wait mode peripheral function clock stop bit (bit 2 of the address 0006 16 ), oscillation stop will be detected. do not stop the peripheral function clock in wait mode.
oscillation stop detection under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 31 b7 b6 b5 b4 b3 b2 b1 b0 rw cm20 cm21 cm22 cm23 0 00 0 oscillation stop detection register (note 5) symbol a ddress when reset cm2 000c 16 04 16 bit name function bit symbol main clock switch bit oscillation stop detection interrupt enable bit 0: the function is invalid. 1: the function is valid. 0: select x in clock. 1: select ring oscillator. 0: disabled 1: enabled 0: x in oscillating normally 1: x in stopping abnormally oscillation stop detection bit clock monitor bit reserved bit always set to "0" note 1: set to 0 before stopping the oscillation of the main clock (x in -x out ). (stop mode, low power dissipation mode, ring oscillation mode) an oscillation stop is detected if the oscillation of the main clock (x in -x out ) is stopped when the following two conditions are satisfied: (1) the oscillation stop detection function is valid and (2) cm21=1. note 2: valid when cm20=1. note 3: cm22 bit switches to 1 automatically if an oscillation stop is detected when both cm20 bit and cm 21 bit are 1. cm22 bit cannot be cleared when cm23=1. note 4: this bit is valid when cm20 bit is 1. use this bit for the purpose of confirming x in operation for oscillation stop detection interrupt execution. note 5: in case of writing to this register, set bit 0 of the protect register(000a 16 ) to "1". (note 3) (note 2) (note 1) (note 4) f main cm22 cm21 oscillation stop detection interrupt generating circuit charge/discharge circuit ring oscillator to the cpu watchdog timer interrupt main clock main clock switch control to the main clock division circuit compulsory discharge when cm20=0 pulse generation circuit for clock edge detection and charge/ discharge control #:when x in is supplied, this repeats charge and discharge with pulses by x in edge detection. when x in is not supplied, this continues charging. when the charge exceeds a certain level, it regards the oscillation as stopped. cm14 (note) note: as for the f main , refer to figure 1.8.3 clock generating circuit. figure 1.10.1. oscillation stop detection circuit figure 1.10.2. oscillation stop detection register
oscillation stop detection under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 32 oscillation stop detection bit (cm20) you can start the oscillation stop detection by setting this bit to "1" and cm21=1 (oscillation stop detection interrupt enabled). the detection is not executed when this bit is set to "0" or in reset status. be sure to set this bit to "0" before setting for the stop-mode. set this bit again to "1" after release from stop-mode. set this bit to "0" also before setting the main clock stop bit (bit 5 at 0006 16 ) to "1". do not set this bit to "1" if the frequency of x in is lower than 2 mhz. an oscillation stop is detected if cm02=1 (peripheral function clock has been set for stop in wait mode) and the mode is shifted to wait. oscillation stop detection interrupt enable bit (cm21) when cm20=1 and cm21=1, an oscillation stop detection interrupt is generated if an abnormal stop of x in is detected. the ring oscillator starts operation instead of the x in clock which stopped abnormally. the operation goes further with the main clock supplied from the ring oscillator. for the oscillation stop detection interrupt, judgment on the interrupt condition is necessary, because this interrupt shares the vector table with watchdog timer interrupt. figure 1.10.3 shows flow of the judgment with oscillation stop detection interrupt processing program. main clock switch bit (cm22) when setting this bit to "1", the ring oscillator is selected as main clock. at this time, the ring oscillator starts simultaneously if it has been stopped (cm14=1). this bit is cleared only when cm23 is "0" (when x in is oscillating). if an oscillation stop is detected while both cm20 and cm21 are 1, this bit automatically switches to 1. when this bit is set to 1, the ring oscillation stop bit (bit 4 of address 0007 16 ) is automatically set to 0. clock monitor bit (cm23) you can see the operation status of the x in clock. when this bit is "0", x in is operating correctly. you can check the oscillation status of x in when an oscillation stop detection interrupt is generated or after reset. when oscillation stop detection is invalid (cm20=0), the clock monitor bit is 0.
oscillation stop detection under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 33 cm23=1? yes no cm21=1 and cm22=1? yes no oscillation stop detection interrupt or watchdog timer interrupt is generated read oscillation stop detection register clear cm21 bit (note) jump to the execution program for oscillation stop detection interrupt jump to the execution program for watchdog timer interrupt note: disables multiple interrupts of oscillation stop detection and let watchdog timer take priority. figure 1.10.3. flow of the judgment
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 34 protection protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 1.11.1 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ) and port p0 direction register (address 00e2 16 ) can only be changed when the respective bit in the protect register is set to 1. there- fore, important outputs can be allocated to port p0. if, after "1" (write-enabled) has been written to bit "enables writing to port p0 direction register" (bit 2 at address 000a 16 ), a value is written to any address, the bit automatically reverts to "0" (write-inhibited). the system clock control registers 0 and 1 and oscillation stop detection register write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit namebit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1(addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) and oscillation stop detection register (address 000 c 16 ) enables writing to port p0 direction register (address 00e2 16 ) (note ) 0 : write-inhibited 1 : write-enabled wr nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. note: writing a value to an address after 1 is written to this bit returns the bit to 0 . other bits do not automatically return to 0 and they must therefore be reset by the program. a a a a a a a a figure 1.11.1. protect register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 35 ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. special peripheral i/o *1 overview of interrupt type of interrupts figure 1.12.1 lists the types of interrupts. figure 1.12.1. classification of interrupts undefined instruction (und instruction) overflow (into instruction) brk instruction _______ int instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? software hardware interrupt ? ? ? ? ? ? ? ? ? ? ? ? reset ________ dbc oscillation stop detection/watchdog timer single step address matched uart0 receive interrupt *1 peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 36 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub brk interrupt a brk interrupt occurs when executing the brk instruction. _______ int interrupt _______ an int interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the _______ int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o interrupts, so _______ executing the int instruction allows executing the same interrupt routine that a peripheral i/o interrupt does. _______ the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt request. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 37 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. reset ____________ reset occurs if an l is input to the reset pin. uart0 receive interrupt uart0 receive interrupt occurs when uart1 is received. this interrupt can be enabled with bit 2 of _______ the int0 input filter select register (address 001e 16 ). this interrupt is exclusively for the debugger, do not use it in other circumstances. _______ dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. oscillation stop detection/watchdog timer interrupt generated by the oscillation stop detection or watchdog timer. single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. the interrupt vector table is _______ the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. key-input interrupt ___ a key-input interrupt occurs if a falling or rising edge is input to the ki pin. a-d conversion interrupt this is an interrupt that the a-d converter generates. uart0 and uart1 transmission interrupt these are interrupts that the serial i/o transmission generates. uart0 and uart1 reception interrupt these are interrupts that the serial i/o reception generates. timer x interrupt this is an interrupts that timer x generates. timer y interrupt this is an interrupt that timer y generates. timer z interrupt this is an interrupt that timer z generates. timer c interrupt this is an interrupt that timer c generates. cntr0 interrupt this interrupt occurs if a falling or rising edge is input to the cntr0 pin. tcin interrupt this interrupt occurs if a falling edge, rising edge or both edges are input to the tcin pin. this interrupt also occurs with the ring512. ________ _______ int0 to int3 interrupt ______ _______ int0 to int2 interrupts occur if any one of a rising edge, a falling edge or a both-edge is input to the ______ _______ ______ int pin. int3 inerrupt occurs if either a falling edge or a both-edge is input to the int pin.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 38 interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector is filled with ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use oscillation stop detection/ ffff0 16 to ffff3 16 watchdog timer ________ dbc (note) ffff4 16 to ffff7 16 do not use uart0 receive (note) ffff8 16 to ffffb 16 do not use reset ffffc 16 to fffff 16 table 1.12.1. interrupt and fixed vector address note: interrupts used for debugging purposes only. aaaaaaaa aaaaaaaa mid address aaaaaaaa aaaaaaaa low address aaaaaaaa aaaaaaaa 0 0 0 0 high address aaaaaaaa aaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 1.12.2 shows format for specifying interrupt vector addresses. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 1.12.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. figure 1.12.2. format for specifying interrupt vector addresses
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 39 software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked by i flag +0 to +3 (note) brk instruction software interrupt number 0 +52 to +55 (note)software interrupt number 13 +56 to +59 (note)software interrupt number 14 +68 to +71 (note)software interrupt number 17 +72 to +75 (note)software interrupt number 18 +76 to +79 (note)software interrupt number 19 +80 to +83 (note)software interrupt number 20 +84 to +87 (note)software interrupt number 21 +88 to +91 (note)software interrupt number 22 +92 to +95 (note)software interrupt number 23 +96 to +99 (note)software interrupt number 24 +100 to +103 (note) software interrupt number 25 +104 to +107 (note) software interrupt number 26 +108 to +111 (note) software interrupt number 27 +112 to +115 (note) software interrupt number 28 +116 to +119 (note) software interrupt number 29 +120 to +123 (note) software interrupt number 30 +124 to +127 (note) software interrupt number 31 +128 to +131 (note) software interrupt number 32 +252 to +255 (note) software interrupt number 63 to note : address relative to address in interrupt table register (intb). to key input interrupt a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer 1 timer x timer y timer z tcin timer c int0 int1 software interrupt cannot be masked by i flag cntr0 int3 int2 variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the address the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 1.12.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. table 1.12.2. interrupt causes (variable interrupt vector addresses)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 40 interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level select bit, and processor interrupt priority level (ipl). whether an interrupt request is present or absent is indi- cated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 1.12.3 shows the interrupt control registers.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 41 symbol address when reset intiic(i=0, 1, 2) 005d 16 , 005e 16 xx00x000 2 005f 16 xx00x000 2 bit name functionbit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. (note 1) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa aa aa a a bit name function bit symbol wr symbol address when reset kupic 0 04d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 sitic(i=0, 1) 0051 16 , 0053 16 xxxxx000 2 siric(i=0, 1) 0052 16 , 0054 16 xxxxx000 2 t1ic 0055 16 xxxxx000 2 txic 0056 16 xxxxx000 2 tyic 0057 16 xxxxx000 2 tzic 0058 16 xxxxx000 2 cntr0ic 0059 16 xxxxx000 2 tcinic 005a 16 xxxxx000 2 tcic 005b 16 xxxxx000 2 int3ic 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. (note 1) note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a figure 1.12.3. interrupt control register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 42 interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 1.12.3 shows the settings of interrupt priority levels and table 1.12.4 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another. table 1.12.3. settings of interrupt priority levels table 1.12.4. interrupt levels enabled according to the contents of the ipl
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 43 rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear t1ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear t1ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear t1ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset changing the interrupt request bit when attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : mov
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 44 instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the instruction sequence is executed. interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16 . after this, the corresponding interrupt request bit becomes "0". (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt se- quence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) _______ to 0 (the u flag, however, does not change if the int instruction, in software interrupt numbers 32 through 63, is executed). (4) saves the content of the temporary register (note) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occur- rence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 1.12.4 shows the interrupt response time. figure 1.12.4. interrupt response time
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 45 interrupt sources without priority levels 7 value set in the ipl watchdog timer other not changed 0 reset ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. interrupt vector address without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) stack pointer (sp) value indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 16 indeterminate s p-2 sp-4 v ec vec+2 pc bclk address bus data bus w r time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 1.12.5. variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 1.12.6 is set in the ipl. figure 1.12.5. time required for executing the interrupt sequence table 1.12.5. time required for executing the interrupt sequence table 1.12.6. relationship between interrupts without interrupt priority levels and ipl
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 46 address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m C 1 m C 2 m C 3 m C 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m C 1 m C 2 m C 3 m C 4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m ) saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 low- order bits of the flg register, 16 bits in total, in the stack area, then saves 16 low-order bits of the program counter. figure 1.12.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). figure 1.12.6. state of stack before and after acceptance of interrupt request
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 47 (2) stack pointer (sp) contains odd number [sp] (odd) [sp] C 1 (even) [sp] C 2(odd) [sp] C 3 (even) [sp] C 4(odd) [sp] C 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] C 1(odd) [sp] C 2 (even) [sp] C 3(odd) [sp] C 4 (even) [sp] C 5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (note), at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 1.12.7 shows the operation of the saving registers. note: this is the stack pointer indicated by the u flag. figure 1.12.7. operation of saving registers
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 48 returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process re- sumes. return the other registers saved by software within the interrupt routine using the popm or similar in- struction before executing the reit instruction. interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 1.12.8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. interrupt priority level judge circuit this circuit selects the interrupt with the highest priority level when two or more interrupts are generated simultaneously. figure 1.12.9 shows the interrupt resolution circuit.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 49 timer z timer c cntr0 a-d conversion timer 1 uart1 transmission uart0 transmission key input interrupt processor interrupt priority level (ipl) interrupt enable flag (i flag) timer x int2 oscillation stop detection/watchdog timer uart0 reception(note) dbc(note) interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) address match uart0 receive hardware interrupt enable bit int0 tcin int1 int3 timer y uart1 reception uart0 reception reset interrupt request level judgment output signal note. interrupts used for debugging purposes only. ________ reset > uart0 receive > dbc > oscillation stop detection/watchdog timer > peripheral i/o > single step > address match figure 1.12.8. hardware interrupts priorities figure 1.12.9. interrupt resolution circuit
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 50 external input enable register bit name function bit symbol wr symbol address when reset inten 0096 16 00 16 int0en b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa aa aa a a int0 input enable bit 0 : disabled 1 : enabled 0 : one edge 1 : two edges 0 : disabled 1 : enabled 0 : one edge 1 : two edges 0 : disabled 1 : enabled int0 input polarity select bit int1 input enable bit int1 input polarity select bit int2 input enable bit int2 input polarity select bit 0 : one edge 1 : two edges int0pl int1en int1pl int2en int2pl a aa a aa a aa a aa a a aa aa a a aa aa int3 input enable bit 0 : disabled 1 : enabled int3en int3 input polarity select bit 0 : one edge 1 : two edges int3pl a aa a aa int0 input filter select register bit name function bit symbol wr symbol address when reset int0f 001e 16 xxxxx000 2 int0f0 b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa aa aa a a int0 input filter select bit 0 0 : no filter 0 1 : filter with f 1 sampling 1 0 : filter with f 8 sampling 1 1 : filter with f 32 sampling 0 : disabled 1 : enabled uart0 receive hardware interrupt enable bit (note) int0f1 int0f2 a aa a a aa aa b1 b0 note: interrupts used for debugging purposes only. ee (note) (note) note : this bit must be set in condition of int0 pin one-shot trigger invalid (inostg="0"). nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. _____ int interrupt ______ ______ ______ ______ int0 to int3 are triggered by the edges of external inputs. the edge polarity of int0 to int2 is selected using the polarity select bit (bit 4 of addresses 005d 16 , 005e 16 and 005f 16 ). input to int0 is available via filter with three different sampling frequencies. as to external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by ______ setting the inti (i=0 to 3) input polarity select bit of the external input enable register (0096 16 ) to 1. to select both edges, set the polarity switching bit of the corresponding interrupt control register to 0 (falling edge). to select one edge, set the polarity switching bit of the corresponding interrupt control register to _________ either 1 (raising edge) or 0 (falling edge). please note that when one edge is selected using int3, the polarity will be a falling edge. after setting the external input enable register, clear the interrupt request bit, and then enable the corre- sponding input interrupt. moreover, you should write to the external input enable bit only under conditions where the corresponding input interrupt is disabled. figure 1.12.10 shows the external input related registers. figure 1.12.10. external input related registers
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 51 digital filter (input level matches 3x) int0 interrupt request int0 f1 f8 f32 int0 input filter select bit port p45 direction register int0 input enable bit _______ int0 input filter _______ the int0 input has a digital filter which can be sampled by one of three sampling clocks. you select the _______ sampling clock using the int0 input filter select bits, bits 1 and 0. _______ int0 interrupt request occurs when the sampled input level matches three times. when selecting 'sampling with filter', the value of the port p4 5 , if read, will be the value after filtering. _____ figure 1.12.11 shows the int0 input filter. ______ figure 1.12.11. int0 input filter
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 52 cntr0 interrupt a cntr0 interrupt is generated from the selected edge polarity, rising or falling edge, of the cntr0 input signal. the edge polarity is selected using the cntr0 polarity select bit (bit 2 of address 008b 16 ). when using the cntr0 interrupt, the port p1 7 direction register should be set to input. when the pulse output mode of timer x is selected, the cntr0 pin functions as a pulse output pin. in this case, a cntr0 interrupt occurs by a falling or rising edge output from the cntr0 pin. the port p1 7 direc- tion register should also be set to input at this time. figure 1.12.12 shows the timer x mode register. figure 1.12.12 timer x mode register timer x mode register symbol address when reset txmr 008b 16 00000000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode or pulse period measurement mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 txmod2 txs txmod1 r0edg txmod0 txocnt cntr0 polarity switching bit operation mode select bit 0, 1 note 1: in the pulse output mode, the direction register of port p1 7 should be set to input. note 2: this bit should rewrite with inhibiting the cntr0 interrupt. note 3: txedg and txund were added after the product ver.3.0 of the flash memory edition (m30100f3/M30102f3) after the product ver.2.0 of the mask rom edition ( m30100mx/ M30102mx). nothing is assigned to the product before this. a a a a a a a a a a a a a a 0 : rising edge 1 : falling edge timer x count start flag 0 : stops counting 1 : starts counting p3 0 /tx out select bit operation mode select bit 2 0 : except in pulse period measurement mode 1 : pulse period measurement mode a a a a (note 1) function varies with each operation mode (note 2) a a a a txedg txund (note 3) (note 3) timer x under flow flag function varies with each operation mode. effectaul edge reception flag function varies with each operation mode.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 53 tcin interrupt a tcin interrupt is generated from edges of a tcin input signal or after 512 divisions of f ring . to use tcin input signal, set the time measurement input source switching bit (bit 7 of address 009a 16 ) of timer c control register 0 to "0" (tcin). the level of input to tcin pin is sampled by one of three sampling clocks, f1, f8 or f32, selected with the digital filter clock select bit (bits 0 and 1 of address 009b 16 ). the input level is determined when the sampled input level matches three times. (however, if the port p3 3 is read, the value will be the unfiltered value.) the edge polarity of an interrupt can be rising edge, falling edge, or both edges using the time measurement edge trigger select bits (bits 3 and 4 of address 009a 16 ). when triggered after 512 divisions of f ring , set the time measurement input source switching bit (bit 7 of address 009a 16 ) to "1" (ring512). figure 1.12.13 shows the timer c control registers 0 and 1. figure 1.12.13 timer c control registers 0 and 1 timer c control register 0 symbol address when reset tcc0 009a 16 0xx00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : inhibit tcc04 tcc02 tcc01 tcc00 tcc03 nothing is assigned. when write, set "0". when read, their contents are "0". time measurement control bit a a aa aa a aa timer c clock select bit 0 : time measurement disabled 1 : time measurement enabled a a aa aa tcc07 b2 b1 time measurement input edge trigger bit time measurement input source switching bit a aa 0 : tcin 1 : ring512 timer c control register 1 symbol address when reset tcc1 009b 16 xxxxxx11 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 tcc11 tcc10 nothing is assigned. when write, set "0". when read, their contents are "0". a a aa aa 0 0 : rising edge 0 1 : falling edge 1 0 : both edges 1 1 : inhibit b4 b3 0 0 : cannot be used 0 1 : f1 1 0 : f8 1 1 : f32 b1 b0 digital filter clock select bit note 1: change this bit when time measurement is disabled. note 2: when using an external rc circuit for the main clock, f 1 cannot be selected for the timer c clock. note 3: set the ring oscillation stop bit (cm14) to 0 before setting this bit to 1. (note 1) (note 1) (note 1) (note 3) (note) note : input edge becomes active when the same value from tc in pin is sampled three times in succession. (note 2)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 54 (address 004d 16 ) key input interrupt request port p1 0 -p1 3 pull-up select bit pull-up transistor port p1 0 direction register pull-up transistor pull-up transistor pull-up transistor p1 3 /ki 3 p1 2 /ki 2 p1 1 /ki 1 p1 0 /ki 0 interrupt control circuit key input interrupt control register k1 0 input enable bit k1 0 input polarity select bit port p1 1 direction register k1 1 input enable bit k1 1 input polarity select bit port p1 2 direction register k1 2 input enable bit k1 2 input polarity select bit port p1 3 direction register k1 3 input enable bit k1 3 input polarity select bit port p1 3 direction register key input enable register bit name function bit symbol wr symbol address when reset kien 0098 16 00 16 ki0en b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa aa aa a a ki0 input enable bit 0 : disabled 1 : enabled 0 : falling edge 1 : rising edges 0 : disabled 1 : enabled 0 : falling edge 1 : rising edges 0 : disabled 1 : enabled ki0 input polarity select bit ki1 input enable bit ki1 input polarity select bit ki2 input enable bit ki2 input polarity select bit 0 : falling edge 1 : rising edges ki0pl ki1en ki1pl ki2en ki2pl aa aa a a aa a aa a aa a aa a aa aa a a ki3 input enable bit 0 : disabled 1 : enabled ki3en ki3 input polarity select bit 0 : falling edge 1 : rising edges ki3pl aa a aa a key input interrupt when the direction register of any of p1 0 to p1 3 is set for input and the kii (i=0 to 3) input enable bit of this port is set for enabled, if a falling or rising edge is input to that port, a key input interrupt is generated. a key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. figure 1.12.14 shows the block diagram of the key input interrupts. when the appropriate signal (l for a pin that has falling edge selected and h for a pin that has rising edge selected) is input to a pin for the input inhibit process has not been executed, inputs to the other pins are not detected as interrupts. you should overwrite the kii (i=0 to 3) input polarity select bit or the kii (i =0 to 3) input enable bit only under conditions where the key input interrupt is disabled. after overwriting the kii (i=0 to 3) input polarity select bit or the kii (i=0 to 3) input enable bit, clear the interrupt request bit, and then enable the key input interrupt. figure 1.12.14. block diagram of key input interrupt figure 1.12.15. key input enable register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 55 bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function wr aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 wr address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) a a a a a a a a a a address match interrupt an address match interrupt is generated immediately before the instruction at the address indicated by the address match interrupt register is executed. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figure 1.12.16 shows the address match interrupt-related registers. figure 1.12.16. address match interrupt-related registers
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer interrupts 56 set the interrupt priority level to level 0 (disable inti interrupt) set the polarity select bit clear the interrupt request bit to 0 set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) clear the interrupt enable flag to 0 (disable interrupt) set the interrupt enable flag to 1 (enable interrupt) precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. even if the address 00000 16 is read out by software, 0 is set to the enabled highest priority interrupt source request bit. therefore, interrupt can be canceled and unexpected interrupt can occur. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. concerning the first instruction immediately after reset, generating any interrupts is prohibited. (3) external interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int0 to _______ int3 regardless of the cpu operation clock. ________ _______ ? when changing a polarity of pins int0 to int3, the interrupt request bit may become "1". clear the ______ interrupt request bit after changing the polarity. figure 1.12.17 shows the switching condition of int interrupt request. (4) changing interrupt control register see "rewrite the interrupt control register". ______ figure 1.12.17. switching condition of int interrupt request
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer watchdog timer 57 figure 1.13.1. block diagram of watchdog timer watchdog timer the watchdog timer has the function of detecting when the program is out of control. therefore, we recom- mend using the watchdog timer to improve reliability of a system. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt or reset is generated when an underflow occurs in the watchdog timer. a watchdog timer interrupt or reset is selected by bit 2 of the processor mode register 1. when x in is selected for the bclk, bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). when x in is selected in bclk watchdog timer cycle = when x cin is selected in bclk watchdog timer cycle = for example, when bclk is 10mhz and the prescaler division ratio is set to 16, the watchdog timer cycle is approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 1.13.1 shows the block diagram of the watchdog timer. figure 1.13.2 shows the watchdog timer- related registers. write to the watchdog timer start register (address 000e 16 ) reset "pm12=0" watchdog timer interrupt request watchdog timer set to 7fff 16 1/128 1/16 cm07 = 0 wdc7 = 1 cm07 = 0 wdc7 = 0 cm07 = 1 bclk 1/2 prescaler "pm12=1" reset prescaler division ratio (16 or 128) x watchdog timer count (32768) bclk prescaler division ratio (2) x watchdog timer count (32768) bclk
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer watchdog timer 58 watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate wr b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to 0 must always be set to 0 00 aa aa a aa a aa a a figure 1.13.2. watchdog timer control and start registers processor mode register 1 (note 1) symbol address when reset pm1 0005 16 00xxx0x0 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to this bits, write 0. the value, if read, turns out to be indeterminate. reserved bit must always be set to 0 0 note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: after setting this bit to "1", can not change to "0" by software. aa a pm12 wdt interrupt/reset switching bit 0 : watchdog timer interrupt 1 : reset (note 2) aa a 0 0 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. reserved bit must always be set to 0 aa a
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer 59 timer the microcomputer has four 8-bit timers and one 16-bit timer. the four 8-bit timers are timer 1, timer x, timer y, and timer z and each one has an 8-bit prescaler. the 16-bit timer is timer c and has time measurement function. all these timers function independently. the count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading. table 1.14.1 shows functional comparison. timer1 timerx timery timerz timerc configuration 8-bit timer 8-bit timer 8-bit timer 8-bit timer 16-bit with 8-bit with 8-bit with 8-bit with 8-bit free-run prescaler prescaler prescaler prescaler timer count down down down down up count source (note) ?f 1 ?f 1 ?f 1 ?f 1 ?f 1 ?f 8 ?f 8 ?f 8 ?f 8 ?f 8 ?f 32 ?f 32 ?f ring ? tmry underflow ?f 32 ?fc 32 ?fc 32 ?fc 32 ?fc 32 function timer mode ? ? pulse output mode ? ? ? ? event counter mode ? ? ? ? pulse width ? ? ? ? measurement mode pulse period ? ? ? ? measurement mode programmable waveform ?? ? generation mode programmable one-shot ?? ? ? generation mode programmable wait ?? ? ? one-shot generation mode time measurement ?? ? ? input pin ? cntr0 ? _____ int0 tcin cntr0 output pin ? ty out tz out ? tx out tmrx int tmrc int related interrupt tmr1 int tmry int tmrz int cntr0 int tcin int timer stop ? note: when using an external rc circuit for the main clock, f 1 cannot be selected for the count source. table 1.14.1. functional comparison
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer 1 60 figure 1.14.1. block diagram of timer 1 timer 1 timer 1 is an 8-bit timer with an 8-bit prescaler. figure 1.14.1 shows the block diagram of timer 1. the timer constantly counts an internally generated count source (clock source). the count source after reset is set to f 1 . the timer cannot stop counting. table 1.14.2 shows the specifications of timer 1 and figure 1.14.2 shows timer 1 related registers. clock source selection f 1 f 8 f 32 f c32 prescaler 1 (address 0088 16 ) peripheral data bus reload register (8) counter (8) reload register (8) counter (8) timer 1 (address 0089 16 ) timer 1 interrupt request bit f p1 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1)/(m+1) n : set value of prescaler 1, m: set value of timer 1 count start condition after reset count stop condition disable to stop counting interrupt request generation timing when timer 1 underflows read from timer count value can be read out by reading timer 1 register. same applies to prescaler 1 register. write to timer when a value is written to timer 1 register, it is written to both reload register and counter. same applies to prescaler 1 register. table 1.14.2. specifications of timer 1 (timer mode)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer 1 61 figure 1.14.2. timer 1-related register bit name function bit symbol timer x count source select bit b1 b0 txck1 txck0 tyck0 timer y count source select bit tzck0 tyck1 tzck1 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 t1ck1 t1ck0 timer 1 count source select bit timer z count source select bit wr a a a a a a a a a a a a a a a a a a a a note 1: when using an external rc circuit for the main clock, f 1 cannot be selected for the count source. note 2: the waveform extend function cannot be used when selecting f 1 for count source. note 3: when attempting to select ring oscillator output, set the ring oscillation enable bit ( cm14) of the system clock control register (address 0007 16 ) for oscillation enabled. note 4: the waveform extend function cannot be used when selecting timer y underflow and f 1 for count source. note 5: avoid switching a count source, while a counter is inprogness. timer counter should be stopped before switching a count source. timer count source setting register symbol address when reset tcss 008e 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b3 b2 0 0 : f 1 0 1 : f 8 1 0 : ring oscillator output 1 1 : f c32 b5 b4 0 0 : f 1 0 1 : f 8 1 0 : timer y underflow 1 1 : f c32 (note 3) (note 4) (note 2) (note 1) (note 1) (note 1) (note 1) (note 5) (note 5) (note 5) symbol address when reset t1 0089 16 xx 16 wr when set value = m, timer 1 divides the underflow of prescaler 1 by m+1 function values that can be set timer 1 a a aa aa symbol address when reset pre1 0088 16 xx 16 b7 b0 wr when set value = n, prescaler 1 divides the internal count source by n+1 function values that can be set prescaler 1 a aa b7 b0 00 16 to ff 16 00 16 to ff 16
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 62 timer x timer x is an 8-bit timer with an 8-bit prescaler. figure 1.14.3 shows the block diagram of timer x. figures 1.14.4 and 1.14.5 shows the timer x-related registers. timer x has the five operation modes listed as follows: ? timer mode: the timer counts an internal count source (clock source). ? pulse output mode: the timer counts an internal count source and outputs the pulses whose polarity is inverted at the timer the timer underflows. ? event counter mode: the timer counts pulses from an external source. ? pulse width measurement mode: the timer measures an external pulse's pulse width. ? pulse period measurement mode:the timer measures an external pulse's period. clock source selection ? timer ? pulse period measurement ? pulse output f 1 f 8 f 32 ? event counter f c32 toggle flip-flop polarity switching cntr 0 q q t cntr0 interrupt request bit p30/tx out select bit tx out cntr 0 polarity switching bit "1" "0" r ? pulse width measurement pulse output counter (8) reload register (8) counter (8) reload register (8) timer x count start flag prescaler x (address 008c 16 ) timer x (address 008d 16 ) pulse output mode timer x latch write timer x interrupt request bit peripheral data bus f px figure 1.14.3. block diagram of timer x timer x mode register symbol address when reset txmr 008b 16 00000000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode or pulse period measurement mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 txmod2 txs txmod1 r0edg txmod0 txocnt cntr0 polarity switching bit operation mode select bit 0, 1 note 1: in the pulse output mode, the direction register of port p1 7 should be set to input. note 2: this bit should rewrite with inhibiting the cntr0 interrupt. note 3: txedg and txund were added after the product ver.3.0 of the flash memory edition (m30100f3/M30102f3) after the product ver.2.0 of the mask rom edition ( m30100mx/ M30102mx). nothing is assigned to the product before this. aa aa a a aa a a a aa a aa a 0 : rising edge 1 : falling edge timer x count start flag 0 : stops counting 1 : starts counting p3 0 /tx out select bit operation mode select bit 2 0 : except in pulse period measurement mode 1 : pulse period measurement mode aa aa a a (note 1) function varies with each operation mode (note 2) aa aa a a aa aa a a txedg txund (note 3) (note 3) timer x under flow flag function varies with each operation mode. effectaul edge reception flag function varies with each operation mode. figure 1.14.4. timer x-related registers (1)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 63 figure 1.14.5. timer x-related registers (2) bit name function bit symbol timer x count source select bit b1 b0 txck1 txck0 tyck0 timer y count source select bit tzck0 tyck1 tzck1 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 t1ck1 t1ck0 timer 1 count source select bit timer z count source select bit wr aa aa a a aa a aa a aa a aa a aa aa a a aa aa a a aa a note 1: when using an external rc circuit for the main clock, f 1 cannot be selected for the count source. note 2: the waveform extend function cannot be used when selecting f 1 for count source. note 3: when attempting to select ring oscillator output, set the ring oscillation enable bit ( cm14) of the system clock control register (address 0007 16 ) for oscillation enabled. note 4: the waveform extend function cannot be used when selecting timer y underflow and f 1 for count source. note 5: avoid switching a count source, while a counter is inprogness. timer counter should be stopped before switching a count source. timer count source setting register symbol address when reset tcss 008e 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b3 b2 0 0 : f 1 0 1 : f 8 1 0 : ring oscillator output 1 1 : f c32 b5 b4 0 0 : f 1 0 1 : f 8 1 0 : timer y underflow 1 1 : f c32 (note 3) (note 4) (note 2) (note 1) (note 1) (note 1) (note 1) (note 5) (note 5) (note 5) symbol address when reset tx 008d 16 ff 16 wr underflow of prescaler x is counted function values that can be set timer x a a symbol address when reset prex 008c 16 ff 16 b7 b0 wr timer mode internal count source is counted function values that can be set prescaler x a a b7 b0 00 16 to ff 16 00 16 to ff 16 pulse output mode internal count source is counted a a 00 16 to ff 16 event counter mode externally input pulses are counted a a 00 16 to ff 16 pulse width measurement mode pulse width of externally input pulses is measured (internal count source is counted) a a a a 00 16 to ff 16 pulse period measurement mode pulse period of externally input pulses is measured (internal count source is counted) a a 00 16 to ff 16
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 64 (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.14.3) figure 1.14.6 shows the timer x mode register in timer mode. item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1)/(m+1) n : set value of prescaler x, m: set value of timer x count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing when timer x underflows [timer x interruption] cntr0 pin function programmable i/o port, or cntr0 interrupt input pin tx out pin function programmable i/o port read from timer count value can be read out by reading timer x register. same applies to prescaler x register. write to timer when a value is written to timer x register, it is written to both reload register and counter. same applies to prescaler x register. table 1.14.3. specifications of timer mode timer x mode register symbol address when reset txmr 008b 16 00000000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 txmod2 txs txmod1 r0edg txmod0 txocnt invalid in timer mode. when write, set "0". when read, this contents is indeteminate. operation mode select bit 0, 1 a a a a a a a a a a a a a a timer x count start flag 0 : stops counting 1 : starts counting 0 : in timer mode, set to "0" a a a a 0 0 0 0 : in timer mode, set to "0" cntr0 polarity switching bit 0 : rising edge 1 : falling edge 0 (note 1) note 1: this bit should rewrite with inhibiting the cntr0 interrupt. a a a a txedg txund invalid in timer mode. when write, set "0". when read, this contents is indeteminate. figure 1.14.6. timer x mode register in timer mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 65 (2) pulse output mode in this mode, the timer counts an internally generated count source, and outputs from the cntr0 pin a pulse whose polarity is inverted each time the timer underflows. (see table 1.14.4) figure 1.14.7 shows timer x mode register in pulse output mode. item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1)/(m+1) n : set value of prescaler x, m: set value of timer x count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing ? when timer x underflows [timer x interruption] ? rising (r0edg=0) or falling (r0edg=1) of cntr0 output [cntr0 interruption] (note) cntr0 pin function pulse output tx out pin function programmable i/o port or pulse output (inverted waveform of the pulse output from the cntr0 pin) read from timer count value can be read out by reading timer x register. same applies to prescaler x register. write to timer when a value is written to timer x register, it is written to both reload register and counter. same applies to prescaler x register. select function ? pulse output function each time the timer underflows, the tx out pins polarity is reversed ? cntr0 polarity switching function the polarity level at starting of pulse output can be selected to be "high" or "low" with software. note: when setting the timer x mode register to pulse output mode, the cntr0 interrupt request bit becomes "1". thus, when using an cntr0 interrupt, the cntr0 interrupt request bit must be set to "0" after setting the timer x mode register. table 1.14.4. specifications of pulse output mode timer x mode register symbol address when reset txmr 008b 16 00000000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 0 1 : pulse output mode b1 b0 txmod2 txs txmod1 r0edg txmod0 txocnt cntr0 polarity switching bit operation mode select bit 0, 1 note 1: in the pulse output mode, the direction register of port p1 7 must be set to input. note 2: output is set regardless of the setting of the direction register of port p3 0 . note 3: this bit should rewrite with inhibiting the cntr0 interrupt. a aa a aa a aa a aa a aa 0: output starts at "h" (interrupt at rising edge) 1: output starts at "l" (interrupt at falling edge) timer x count start flag 0 : stops counting 1 : starts counting p3 0 /tx out select bit 0 : port p3 0 1 : tx out output 0 : set to "0" in pulse output mode a aa (note 1) (note 2) 0 0 1 (note 3) a aa a a aa aa invalid in pulse output mode. when write, set "0". when read, this contents is indeteminate. txedg txund invalid in pulse output mode. when write, set "0". when read, this contents is indeteminate. figure 1.14.7. timer x mode register in pulse output mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 66 (3) event counter mode in this mode, the timer counts an external signal fed to cntr0 pin. (see table 1.14.5) figure 1.14.8 shows timer x mode register in event counter mode. item specification count source external signals fed to cntr 0 pin (active edge is selected by software) count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1)/(m+1) n : set value of prescaler x, m: set value of timer x count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing ? when timer x underflows [timer x interruption] ? rising (r0edg=0) or falling (r0edg=1) of cntr0 input [cntr0 interruption] cntr0 pin function count source input tx out pin function programmable i/o port read from timer count value can be read out by reading timer x register. same applies to prescaler x register. write to timer when a value is written to timer x register, it is written to both reload register and counter. same applies to prescaler x register. select function ? cntr0 polarity switching function the active edge of count source can be selected to be the rising or the falling edge with software. timer x mode register symbol address when reset txmr 008b 16 00000000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 1 0 : event counter mode b1 b0 txmod2 txs txmod1 r0edg txmod0 txocnt cntr0 polarity switching bit operation mode select bit 0, 1 a aa a aa a aa a aa a aa 0: counts at rising edge (interrupt at rising edge) 1: counts at falling edge(interrupt at falling edge) timer x count start flag 0 : stops counting 1 : starts counting 0 : set to "0" in event counter mode a a aa aa 0 1 0 0 : set to "0" in event counter mode 0 (note 1) note 1: this bit should rewrite with inhibiting the cntr0 interrupt. a a aa aa a aa invalid in event counter mode. when write, set "0". when read, this contents is indeteminate. txedg txund invalid in event counter mode. when write, set "0". when read, this contents is indeteminate. figure 1.14.8. timer x mode register in event counter mode table 1.14.5. specifications of event counter mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 67 table 1.14.6. specifications of pulse width measurement mode (4) pulse width measurement mode in this mode, the timer measures the pulse width of an external signal fed to cntr0 pin. (see table 1.14.6) figure 1.14.9 shows the timer x mode register in pulse width measurement mode. figure 1.14.10 shows an operation example in pulse width measurement mode. item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? continuously counts the selected signal only when the measurement pulse is "h" level, or conversely only "l" level. ? when the timer underflows, it reloads the reload register contents before continuing counting count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing ? when timer x underflows [timer x interruption] ? rising (r0edg=0) or falling (r0edg=1) of cntr0 input [cntr0 interruption] cntr0 pin function measurement pulse input tx out pin function programmable i/o port read from timer count value can be read out by reading timer x register. same applies to prescaler x register. write to timer when a value is written to timer x register, it is written to both reload register and counter. same applies to prescaler x register. select function ? cntr0 polarity switching function the measurement pulse input can be selected to be "h" level width or "l" level width by software. timer x mode register symbol address when reset txmr 008b 16 00000000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 1 1 : pulse width measurement mode b1 b0 txmod2 txs txmod1 r0edg txmod0 cntr0 polarity switching bit operation mode select bit 0, 1 a aa a aa a a aa aa a aa a aa 0 : measures h level width (interrupt at rising edge) 1 : measures l level width (interrupt at falling edge) timer x count start flag 0 : stops counting 1 : starts counting 0 : set to "0" in pulse width measurement mode a aa txocnt 0 1 1 0 : set to "0" in pulse width measurement mode 0 note 1: this bit should rewrite with inhibiting the cntr0 interrupt. (note 1) a aa a aa invalid in pulse width measurement mode. when write, set "0". when read, this contents is indeteminate. txedg txund invalid in pulse width measurement mode. when write, set "0". when read, this contents is indeteminate. figure 1.14.9. timer x mode register in pulse width measurement mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 68 ffff 16 n 0000 16 counter contents n = high-level: the contents of timer x reload register, low-level: the contents of prescaler x reload register count stop set to "1" by software count start underflow count start flag measurement pulse (cntr0 pin input) cntr0 interrupt request bit conditions: "h" level width of measurement pulse is measured. (r0edg=1) 1 0 timer x interrupt request bit cleared to 0 when interrupt request is accepted, or cleared by software h l 1 0 1 0 count stop count restart time cleared to 0 when interrupt request is accepted, or cleared by software figure 1.14.10. operation example in pulse width measurement mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 69 (5) pulse period measurement mode in this mode, the timer measures the pulse period of an external signal fed to cntr0 pin. (see table 1.14.7) figure 1.14.11 shows the timer x mode register in pulse period measurement mode. item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? after valid edge of measurement pulse is input, the timer x reloads contents in the reload register and continues counting in underflow of the second prescaler x. count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing ? when timer x underflows [timer x interruption] ? rising (r0edg=0) or falling (r0edg=1) of cntr0 input [cntr0 interruption or timer x interrupt] cntr0 pin function measurement pulse input (note) tx out pin function programmable i/o port read from timer when reading timer x register, the count value of buffer for read purpose can be read out. the buffer of read purpose retains the content of timer x register upon an active edge of measurement pulse, and starts to read the content of timer x register by read- ing timer x. write to timer when a value is written to timer x register, it is written to both reload register and counter. same applies to prescaler x register. select function ? cntr0 polarity switching function the measurement period of pulse input can be selected to be a period from one rising edge to the next rising edge or from one falling edge to the next falling edge by software. note: avoid a shorter period pulse input than double prescaler x period. longer pulse for h width and l width than the prescaler x period should be input to the cntr0 pin. if shorter pulse than the period is input to the cntr0 pin, the input may be disabled. table 1.14.7. specifications of pulse period measurement mode timer x mode register symbol address when reset txmr 008b 16 00000000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 0 0 : pulse period measurement mode b1 b0 txmod2 txs txmod1 r0edg txmod0 txocnt cntr0 polarity switching bit operation mode select bit 0, 1 a a a a a a a a a a a a 0: measures a measurement pulse from one rising edge to the next rising edge (interrupt at rising edge) 1: measures a measurement pulse from one falling edge to the next falling edge (interrupt at falling edge) timer x count start flag 0 : stops counting 1 : starts counting operation mode select bit 2 1 : pulse period measurement mode a a 1 0 0 0 : in pulse period measurement mode, set to "0" 0 a a a a txedg txund (note 2,3) (note 2,3) timer x under flow flag 0 : no under flow 1 : under flow found 0 : no effectual edge 1 : effectual edge found effectaul edge reception flag note 1: this bit should rewrite with inhibiting the cntr0 interrupt. note 2: txedg and txund are set to "0" by writing a "0" in a program. (writing a "1" has no effect.) note 3: txedg and txund were added after the product ver.3.0 of the flash memory edition (m30100f3/M30102f3) after the product ver.2.0 of the mask rom edition ( m30100mx/ M30102mx). nothing is assigned to the product before this. (note 1) figure 1.14.11. timer x mode register in pulse period measurement mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer x 70 figure 1.14.12. operation example in pulse period measurement mode timer x=0f 16 f px 0f 16 0e 16 0f 16 0e 16 0d 16 0c 16 0b 16 0a 16 0f 16 0e 16 0d 16 01 16 00 16 0f 16 0e 16 0f 16 0e 16 0d 16 0b 16 09 16 timer x reloads 0d 16 01 16 0f 16 0e 16 read by software. (note 3) effectaul edge reception flag (note 2) cleared to "0" by software. timer x underflow flag note 1: if timer x is read out in pulse period measurement mode, the contents of the read purpose buffer can be read. note 2: after an active edge of measurement pulse is input, effectaul edge reception flag(txedg) is set to "1" when the prescaler x underflows for the second time. note 3: the timer x should be read out before the next active edge is input after txedg is set to "1". if the timer x is not read before the next active edge is input, the value in the read purpose buffer remains unchanged and therefore is not updated on an active edge. note 4: when set to "0" by software, use a mov instruction to write "0" to the bit 6 (txedg) in the timer x mode register (008b 16 ). at the same time, write "1" to the bit 7 (txund). note 5: when set to "0" by software, use a mov instruction to write "0" to the bit 7 (txund) in the timer x more register (008b 16 ). at the same time, write "1" to the bit 6 (txedg). note 6: if the timer x underflow flag (txund) and txedg are both set to "1". in this case, the validity of txund sholud be judged by the contents of the read purpose buffer. conditions: a period from one rising edge to the next rising edge of measurement pulse is measured. (r0edg=0) set to "1" by software count start count start flag 1 0 1 0 measurement pulse (cntr0 pin input) timer x contents (hex) contents of read purpose buffer( note 1) timer x reloads timer x reloads read by software. (note 3) (note 2) (note 4) (note 5) (note 6) cleared to "0" by software. 1 0 1 0 1 0 1 0 cleared to 0 when interrupt request is accepted, or cleared by software cleared to 0 when interrupt request is accepted, or cleared by software cntr0 interrupt request bit timer x interrupt request bit 0a 16 00 16 hold hold 09 16 0d 16
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 71 timer y timer y is an 8-bit timer with an 8-bit prescaler and has two reload registers - timer y primary and timer y secondary. figure 1.14.13 shows the block diagram of timer y. figures 1.14.14 to 1.14.16 show the timer y-related registers. timer y has the two operation modes listed as follows: ? timer mode: the timer counts an internal count source (clock source). ? programmable waveform generation mode: the timer outputs pulses of a given width successively. figure 1.14.13. block diagram of timer y figure 1.14.14. timer y-related registers (1) timer y primary (address 0083 16 ) clock source selection f 1 f 8 f ring f c32 toggle flip-flop port p3 2 register timer y programmable waveform output switching bit timer y output level latch programmable waveform generation mode timer y count start flag timer y (address 0083 16 ) timer y interrupt request bit ty out q t "1" "1" q "0" "0" peripheral data bus timer y secondary (address 0082 16 ) counter (8) reload register (8) reload register (8) counter (8) reload register (8) prescaler y (address 0081 16 ) f py timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is "0". timer y operation mode bit note 1: in programmable waveform generation mode, port p3 2 is set for output regardless of the value of the direction register. note 2: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. note 3: when timer z operation mode bit is set for "01", "10" or "11", port p3 1 is set for output regardless of the value of the direction register. a aa a aa a aa a aa a aa timer y write control bit function varies depending on the operation mode 0 : timer mode 1 : programmable waveform generation mode a a aa aa (note 1) (note 3) tzwc tzs 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting timer z count start flag timer z operation mode bit b5 b4 timer y count start flag timer z write control bit a aa (note 2) (note 2) function varies depending on the operation mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 72 timer y, z output control register symbol address when reset tyzoc 008a 16 xxxxx000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 tzocnt tyocnt tzos nothing is assigned. when write, set "0". when read, their contents are "0". timer z one-shot start bit a a a a timer y programmable waveform generation output switching bit 0 : outputs programmable waveform 1 : outputs the value of p3 2 port register 0 : outputs programmable waveform 1 : outputs the value of p3 1 port register 0 : stops one-shot 1 : starts one-shot timer z programmable waveform generation output switching bit a a (note 2) (note 2) note 1: the timer z one-shot start bit is automatically cleared to "0" when the output of one-shot waveform is completed. the timer z one-shot start bit should be set to "0" by program when the one-shot waveform output is terminated by setting the count start flag to "0" during the wave form output. note 2: the timer y/z programmable waveform generaton output switching bit is valid only when operating in programmable waveform generation mode. (note 1) figure 1.14.15. timer y-related registers (2) timer y secondary symbol address when reset prey 0081 16 ff 16 b7 b0 wr ? timer mode internal count source is counted function values that can be set prescaler y aa aa a a 00 16 to ff 16 programmable waveform generation mode internal count source is counted aa a 00 16 to ff 16 (note) note: when using the waveform extend function, set the value "00 16 " for the prescaler y. symbol address when reset tysc 0082 16 ff 16 b7 b0 wr timer mode invalid function values that can be set programmable waveform generation mode underflow of prescaler y is counted 00 16 to ff 16 (note 1) note 1: the values of timer y primary and timer y secondary are reloaded to the timer y alternately for counting. note 2: the count value can be read out by reading the timer y primary even when the secondary period is being counted. timer y primary symbol address when reset typr 0083 16 ff 16 b7 b0 wr timer mode underflow of prescaler y is counted function values that can be set aa a 00 16 to ff 16 programmable waveform generation mode underflow of prescaler y is counted aa a 00 16 to ff 16 (note) note: the values of timer y primary and timer y secondary are reloaded to the timer y alternately for counting. (note 2) a
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 73 bit name function bit symbol timer y primary waveform extension control bit typum1 typum0 tzpum0 tyopl tzpum1 tzopl inoseg inostg int0 pin one-shot trigger polarity select bit timer z output level latch wr a a a a a a a a a a a a a a a a a a a a timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 0 : no waveform extension 1 : waveform extension timer y secondary waveform extension control bit timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y output level latch int0 pin one-shot trigger control bit 0 : no waveform extension 1 : waveform extension 0 : no waveform extension 1 : waveform extension 0 : no waveform extension 1 : waveform extension function varies depending on the operation mode function varies depending on the operation mode 0 : int0 pin one-shot trigger invalid 1 : int0 pin one-shot trigger valid 0 : edge trigger at falling edge 1 : edge trigger at rising edge (timer z) (timer z) (note 3) (note 1) (note 1) (note 2) (note 2) note 1: when setting this bit to "1", the prescaler y register must be set to "00 16 ". note 2: when setting this bit to "1", the prescaler z register must be set to "00 16 ". note 3: this bit is valid only when int0 input polarity select bit (bit 1 at address 0096 16 ) is "0" (one-edge). note 4: this bit must be set to "1", after setting int0 input enable bit (bit 0 at address 0096 16 ), int0 input polarity select bit (bit 1 at address 0096 16 ), and int0 pin one-shot trigger polarity select bit. (note 4) figure 1.14.16. timer y-related registers (3) bit name function bit symbol timer x count source select bit b1 b0 txck1 txck0 tyck0 timer y count source select bit tzck0 tyck1 tzck1 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 t1ck1 t1ck0 timer 1 count source select bit timer z count source select bit wr a a a a a a a a a a a a a a a a a a note 1: when using an external rc circuit for the main clock, f 1 cannot be selected for the count source. note 2: the waveform extend function cannot be used when selecting f 1 for count source. note 3: when attempting to select ring oscillator output, set the ring oscillation enable bit ( cm14) of the system clock control register (address 0007 16 ) for oscillation enabled. note 4: the waveform extend function cannot be used when selecting timer y underflow and f 1 for count source. note 5: avoid switching a count source, while a counter is inprogness. timer counter should be stopped before switching a count source. timer count source setting register symbol address when reset tcss 008e 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b3 b2 0 0 : f 1 0 1 : f 8 1 0 : ring oscillator output 1 1 : f c32 b5 b4 0 0 : f 1 0 1 : f 8 1 0 : timer y underflow 1 1 : f c32 (note 3) (note 4) (note 2) (note 1) (note 1) (note 1) (note 1) (note 5) (note 5) (note 5)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 74 (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.14.8) the timer y secondary is unused in this mode. figure 1.14.17 shows the timer y, z mode register and timer y, z waveform output control register in timer mode. item specification count source f 1 , f 8 , ring oscillator output, f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting (when the timer y underflows, the contents of the timer y primary reload register is reloaded.) ? when a counting stops, the timer reloads the content of the reload register before it stops. divide ratio 1/(n+1)/(m+1) n : set value of prescaler y, m: set value of timer y primary count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) (note 1) interrupt request generation timing when timer y underflows ty out pin function programmable i/o port read from timer count value can be read out by reading timer y primary register. same applies to prescaler y register. write to timer when a value is written to timer y primary register, it is written to both reload register and counter or written to only reload register. selected by software. same applies to prescaler y register. select function ? timer y write control function when a value is written to timer y primary register, it can be selected that the value is written to both reload register and counter or written to only reload register. same applies to prescaler z register. (note 2) note 1: when the count is stopped, the timer y interrupt request flag becomes "1" and an interrupt may occur. thus, interrupts must be disabled before the count is stopped. furthermore, set the timer y interrupt request flag to "0" before starting counting again. note 2: if writing to the timer y or prescaler y under the following conditions being filled at the same time the timer y interrupt request flag becomes "1" and an interrupt occurs. ? timer y write control bit (bit 2 of address 0080) is "0" (write to timer and reload register simultaneously) ? timer y count start flag (bit 3 of address 0080) is "1" (count start) to write to the timer y or prescaler y in the above state, disable interrupts before writing. table 1.14.8. specifications of timer mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 75 figure 1.14.17. timer y, z mode register in timer mode timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is indeterminate. timer y operation mode bit note 1: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. note 2: at the tywc bit is "0", when you write in the prescaler y while the timer y is counting,the timer y reload content of the timer y reload register. aa aa a a aa a aa a aa a aa aa a a timer y write control bit 0 : write to timer and reload register simultaneously 1 : write to reload register 0 : timer mode aa a tzwc tzs 0 : stops counting 1 : starts counting timer z-related bit timer y count start flag aa a (note 1) 0 (note 2) bit name function bit symbol timer y primary waveform extension control bit typum1 typum0 tzpum0 tyopl tzpum1 tzopl inoseg inostg timer z-related bits wr aa a aa aa a a aa a aa aa a a aa a aa a aa a aa a timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 invalid in timer mode timer y secondary waveform extension control bit timer z-related bits timer y output level latch invalid in timer mode invalid in timer mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 76 (2) programmable waveform generation mode in this mode, the microcontroller, while counting the set values of timer y primary and timer y sec- ondary alternately, outputs from the ty out pin a waveform whose polarity is inverted each time timer y primary or timer y secondary underflows. (see table 1.14.9) a counting starts by counting the set value in the timer y primary. figure 1.14.18 shows timer y, z mode register in programmable wave- form generation mode. figure 1.14.19 shows the operation example. item specification count source f 1 , f 8 , ring oscillator output, f c32 count operation ? down count ? when the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting. ? when a counting stops, the timer reloads the content of the reload register before it stops. divide ratio fi/(n+1)/((m+1)+(l+1)) n : set value of prescaler y, m: set value of timer y primary, l: set value of timer y secondary count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) (note 1) interrupt request generation timing when timer y underflows during secondary period ty out pin function pulse output (note 2) read from timer count value can be read out by reading timer y primary register. same applies to prescaler y register. (note 3) write to timer when a value is written to timer y primary register, it is written to only reload register. same applies to timer y secondary register and prescaler y register. (note 4) select function ? output level latch select function the output level of a waveform being counted during primary and secondary periods is selectable. ? programmable waveform generation output switching function can select either programmable waveform or the value of port p3 2 register for output. (note 5) ? waveform extend function (note 6) the waveform output primary period and secondary period can each be extended 0.5 cycles of the count source frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+typum0+typum1) duty: (2x(m+1)+typum0)/((2x(m+1)+typum0)+(2x(l+1)+typum1)) m: set value of timer y primary, l: set value of timer y secondary typum0: timer y primary waveform extension control bit typum1: timer y secondary waveform extension control bit note 1: when the count is stopped, the timer y interrupt request flag becomes "1" and an interrupt may occur. thus, interrupts must be disabled before the count is stopped. furthermore, set the timer y interrupt request flag to "0" before starting counting again. note 2: when the counting stopped, the pin is the secondary period output level. note 3: even when counting the secondary period, read out the timer y primary register. note 4: the set value of timer y secondary register and waveform extension control bits as well as timer y primary register are made effective by writing a value to the timer y primary register. the written values are reflected to the waveform output from the next primary period after writing to the timer y primary register. note 5: the output is switched in sync with timer y secondary underflow. note 6: when using the waveform extend function, the prescaler y register must be set to "00 16 ". table 1.14.9. specifications of programmable waveform generation mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 77 figure 1.14.18. timer y, z mode register and timer y, z waveform output control register in programmable waveform generation mode timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is indeterminate. timer y operation mode bit note 1: output is set for port p3 2 regardless of the value of the direction register. note 2: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. a aa a aa a aa a a aa aa a aa set to "1" in programmable waveform generation mode 1 : programmable waveform generation mode a aa tzwc tzs 0 : stops counting 1 : starts counting timer z-related bit timer y count start flag a aa (note 2) 1 1 (note 1) timer y write control bit bit name function bit symbol timer y primary waveform extension control bit typum1 typum0 tzpum0 tyopl tzpum1 tzopl inoseg inostg timer z-related bits wr aa a aa a aa aa a a aa aa a a aa a aa aa a a aa a aa a timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer y secondary waveform extension control bit timer z-related bits timer y output level latch 0 : no waveform extension 1 : waveform extension (note 1) 0 : no waveform extension 1 : waveform extension (note 1) 0 : outputs "h" for the period set by timer y primary and "l" for the period set by timer y secondary. "l" is outputted when the timer is stopped. 1 : outputs "l" for the period set by timer y primary and "h" for the period set by timer y secondary. "h" is outputted when the timer is stopped. note 1: when setting this bit to "1", the prescaler y register must be set to "00 16 ". note 2: the waveform extend function cannot be used when selecting f 1 for count source. (note 2) (note 2)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer y 78 set to "1" by software count start flag the contents of timer y ty out pin output conditions: timer y primary=03 16 , timer y primary waveform not extended, timer y secondary=02 16 , timer y secondary waveform extended, timer y output level latch [tyopl]="0" 1 0 timer y interrupt request bit h l 1 0 1 0 a a 02 16 03 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 count start timer y count source timer y output level latch cleared to "0" by software timer y secondary reload timer y primary reload timer y secondary reload cleared to 0 when interrupt request is accepted, or cleared by software waveform output started waveform output inverted waveform output inverted waveform output inverted initialized to "l" secondary waveform extended (note) note: the waveform output in the secondary period is inverted after 0.5 clock ( 1 clock when secondary waveform extended) of f py from occurrence of timer y interrupt request. figure 1.14.19. timer y operation example in programmable waveform generation mode programmable waveform generation output switching function when the timer y programmable waveform generation output switching bit (bit 1 at address 008a 16 ) is set to 0, the output from ty out is inverted synchronously when the timer y secondary underflows. and when set to 1, the port p3 2 register value is output from ty out synchronously when the timer y secondary underflows.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 79 timer z primary (address 0087 16 ) clock source selection f 1 f 8 timer y underflow f c32 toggle flip-flop port p3 1 register timer z programmable timer z output level latch ?programmable waveform generation mode ?programmable one-shot generation mode ?programmable wait one-shot generation mode timer z count start flag timer z interrupt request bit timer z secondary (address 0086 16 ) tz out int0 q t "0" "1" "1" q "0" peripheral data bus reload register (8) reload register (8) reload register (8) timer z (address 0087 16 ) counter (8) counter (8) prescaler z (address 0085 16 ) ?programmable one-shot generation mode ?programmable wait one-shot generation mode timer z one-shot start bit int0 input enable bit int0 input polarity select bit one edge/ both edges input polarity select digital filter polarity select int0 one-shot trigger polarity select bit f pz figure 1.14.20. block diagram of timer z timer z timer z is an 8-bit timer with an 8-bit prescaler and has two reload registers - timer z primary and timer z secondary. figure 1.14.20 shows the block diagram of timer z. figures 1.14.21 to 1.14.24 show the timer z-related registers. timer z has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source (clock source) or timer y underflow. ? programmable waveform generation mode: the timer outputs pulses of a given width successively. ? programmable one-shot generation mode: the timer outputs one-shot pulse. ? programmable wait one-shot generation mode: the timer outputs delayed one-shot pulse.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 80 timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is "0". timer y operation mode bit note 1: in programmable waveform generation mode, port p3 2 is set for output regardless of the value of the direction register. note 2: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. note 3: when timer z operation mode bit is set for "01", "10" or "11", port p3 1 is set for output regardless of the value of the direction register. a a a a a a a a a a a a a a a a timer y write control bit function varies depending on the operation mode 0 : timer mode 1 : programmable waveform generation mode a a (note 1) (note 3) tzwc tzs 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting timer z count start flag timer z operation mode bit b5 b4 timer y count start flag timer z write control bit a a (note 2) (note 2) function varies depending on the operation mode figure 1.14.21. timer z-related registers (1)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 81 figure 1.14.22. timer z-related registers (2) timer z secondary symbol address when reset prez 0085 16 ff 16 b7 b0 wr ? timer mode internal count source or timer y underflow is counted function values that can be set prescaler z a a aa aa 00 16 to ff 16 programmable waveform generation mode internal count source or timer y underflow is counted a aa 00 16 to ff 16 (note) note: when using the waveform extend function, set the value "00 16 " for the prescaler z. symbol address when reset tzsc 0086 16 ff 16 b7 b0 wr timer mode invalid function values that can be set programmable waveform generation mode underflow of prescaler z is counted 00 16 to ff 16 (note 1) note 1: each value of timer z primary and timer z secondary is reloaded to the timer z alternately for counting. note 2: the count value can be read out by reading the timer z primary even when the secondary period is being counted. timer z primary symbol address when reset tzpr 0087 16 ff 16 b7 b0 wr timer mode underflow of prescaler z is counted function values that can be set a aa 00 16 to ff 16 programmable waveform generation mode underflow of prescaler z is counted a a aa aa 00 16 to ff 16 (note) note: each value of timer z primary and timer z secondary is reloaded to the timer z alternately for counting. (note 2) a programmable one-shot generation mode internal count source or timer y underflow is counted a aa 00 16 to ff 16 (note) programmable wait one-shot generation mode internal count source or timer y underflow is counted a aa 00 16 to ff 16 (note) programmable one-shot generation mode invalid programmable wait one-shot generation mode underflow of prescaler z is counted (one-shot width is counted) 00 16 to ff 16 a programmable one-shot generation mode underflow of prescaler z is counted (one-shot width is counted) a aa 00 16 to ff 16 programmable wait one-shot generation mode underflow of prescaler z is counted (wait period is counted) a a aa aa 00 16 to ff 16
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 82 figure 1.14.23. timer z-related registers (3) bit name function bit symbol timer y primary waveform extension control bit typum1 typum0 tzpum0 tyopl tzpum1 tzopl inoseg inostg int0 pin one-shot trigger polarity select bit timer z output level latch wr aa a aa a aa a aa a aa aa a a aa a aa aa a a aa a timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 0 : no waveform extension 1 : waveform extension timer y secondary waveform extension control bit timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y output level latch int0 pin one-shot trigger control bit 0 : no waveform extension 1 : waveform extension 0 : no waveform extension 1 : waveform extension 0 : no waveform extension 1 : waveform extension function varies depending on the operation mode function varies depending on the operation mode 0 : int0 pin one-shot trigger invalid 1 : int0 pin one-shot trigger valid 0 : edge trigger at falling edge 1 : edge trigger at rising edge (timer z) (timer z) (note 3) (note 1) (note 1) (note 2) (note 2) note 1: when setting this bit to "1", the prescaler y register must be set to "00 16 ". note 2: when setting this bit to "1", the prescaler z register must be set to "00 16 ". note 3: this bit is valid only when int0 input polarity select bit (bit 1 at address 0096 16 ) is "0" (one-edge). note 4: this bit must be set to "1", after setting int0 input enable bit (bit 0 at address 0096 16 ), int0 input polarity select bit (bit 1 at address 0096 16 ), and int0 pin one-shot trigger polarity select bit. (note 4) bit name function bit symbol timer x count source select bit b1 b0 txck1 txck0 tyck0 timer y count source select bit tzck0 tyck1 tzck1 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 t1ck1 t1ck0 timer 1 count source select bit timer z count source select bit wr aa a aa a aa a aa a aa a aa aa a a aa a aa aa a a note 1: when using an external rc circuit for the main clock, f 1 cannot be selected for the count source. note 2: the waveform extend function cannot be used when selecting f 1 for count source. note 3: when attempting to select ring oscillator output, set the ring oscillation enable bit ( cm14) of the system clock control register (address 0007 16 ) for oscillation enabled. note 4: the waveform extend function cannot be used when selecting timer y underflow and f 1 for count source. note 5: avoid switching a count source, while a counter is inprogness. timer counter should be stopped before switching a count source. timer count source setting register symbol address when reset tcss 008e 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b3 b2 0 0 : f 1 0 1 : f 8 1 0 : ring oscillator output 1 1 : f c32 b5 b4 0 0 : f 1 0 1 : f 8 1 0 : timer y underflow 1 1 : f c32 (note 3) (note 4) (note 2) (note 1) (note 1) (note 1) (note 1) (note 5) (note 5) (note 5)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 83 figure 1.14.24. timer z-related registers (4) timer y, z output control register symbol address when reset tyzoc 008a 16 xxxxx000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 tzocnt tyocnt tzos nothing is assigned. when write, set "0". when read, their contents are "0". timer z one-shot start bit a a a a a a timer y programmable waveform generation output switching bit 0 : outputs programmable waveform 1 : outputs the value of p3 2 port register 0 : outputs programmable waveform 1 : outputs the value of p3 1 port register 0 : stops one-shot 1 : starts one-shot timer z programmable waveform generation output switching bit a a a a (note 2) (note 2) note 1: the timer z one-shot start bit is automatically cleared to "0" when the output of one-shot waveform is completed. the timer z one-shot start bit should be set to "0" by program when the one-shot waveform output is terminated by setting the count start flag to "0" during the wave form output. note 2: the timer y/z programmable waveform generaton output switching bit is valid only when operating in programmable waveform generation mode. (note 1) external input enable register bit name function bit symbol wr symbol address when reset inten 0096 16 00 16 int0en b7 b6 b5 b4 b3 b2 b1 b0 aa a aa a int0 input enable bit 0 : disabled 1 : enabled 0 : one edge 1 : two edges 0 : disabled 1 : enabled 0 : one edge 1 : two edges 0 : disabled 1 : enabled int0 input polarity select bit int1 input enable bit int1 input polarity select bit int2 input enable bit int2 input polarity select bit 0 : one edge 1 : two edges int0pl int1en int1pl int2en int2pl aa aa a a aa a aa a aa a aa aa a a aa aa a a int3 input enable bit 0 : disabled 1 : enabled int3en int3 input polarity select bit 0 : one edge 1 : two edges int3pl aa a aa a int0 input filter select register bit name function bit symbol wr symbol address when reset int0f 001e 16 xxxxx000 2 int0f0 b7 b6 b5 b4 b3 b2 b1 b0 aa a aa a int0 input filter select bit 0 0 : no filter 0 1 : filter with f 1 sampling 1 0 : filter with f 8 sampling 1 1 : filter with f 32 sampling 0 : disabled 1 : enabled uart0 receive hardware interrupt enable bit (note) int0f1 int0f2 aa aa a a aa a b1 b0 note: interrupts used for debugging purposes only. ee (note) (note) note : this bit must be set in condition of int0 pin one-shot trigger invalid (inostg="0"). nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 84 (1) timer mode in this mode, the timer counts an internally generated count source or timer y underflow. (see table 1.14.10) the timer z secondary is unused in this mode. figure 1.14.25 shows the timer y, z mode register and timer y, z waveform output control register in timer mode. item specification count source f 1 , f 8 , timer y underflow, f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting (when the timer z underflows, the contents of the timer z primary reload register is reloaded.) ? when a counting stops, the timer reloads the content of the reload register before stopping counting. divide ratio 1/(n+1)/(m+1) n : set value of prescaler z, m: set value of timer z primary count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) (note 1) interrupt request generation timing when timer z underflows ty out pin function programmable i/o port _______ int0 pin function programmable i/o port, or external interrupt input pin read from timer count value can be read out by reading timer z primary register. same applies to prescaler z register. write to timer when a value is written to timer z primary register, it is written to both reload register and counter or written to only reload register. selected by software. same applies to prescaler z register. select function ? timer z write control function when a value is written to timer z primary register, it can be selected that the value is written to both reload register and counter or written to only reload register. same applies to prescaler z register. (note 2) note 1: when the count is stopped, the timer z interrupt request flag becomes "1" and an interrupt may occur. thus, interrupts must be disabled before the count is stopped. furthermore, set the timer z interrupt request bit to "0" before starting counting again. note 2: if writing to the timer z or prescaler z under the following conditions being filled at the same time the timer z interrupt request flag becomes "1" and an interrupt occurs. ? timer z write control bit (bit 6 of address 0080) is "0" (write to timer and reload register simultaneously) ? timer z count start flag (bit 7 of address 0080) is "1" (count start) to write to the timer z or prescaler z in the above state, disable interrupts before writing. table 1.14.10. specifications of timer mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 85 figure 1.14.25. timer y, z mode register and timer y, z waveform output control register in timer mode timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is "0". timer y-related bit note 1: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. note 2: at the tzwc bit is "0", when you write in the prescaler z while the timer z is counting,the timer z reload content of the timer z reload register. aa a aa a aa aa a a aa a aa a timer y-related bits aa aa a a tzwc tzs 0 : stops counting 1 : starts counting timer z count start flag timer z operation mode bit b5 b4 timer z write control bit aa a 0 : write to timer and reload register simultaneously 1 : write to reload register (note 1) 0 0 (note 2) bit name function bit symbol timer y-related bits typum1 typum0 tzpum0 tyopl tzpum1 tzopl inoseg inostg int0 pin one-shot trigger polarity select bit timer z output level latch wr a aa a aa a aa a aa a aa a aa a aa a aa timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y-related bit int0 pin one-shot trigger control bit invalid in timer mode invalid in timer mode invalid in timer mode invalid in timer mode invalid in timer mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 86 (2) programmable waveform generation mode in this mode, the microcontroller, while counting the set values of timer z primary and timer z sec- ondary alternately, outputs from the tz out pin a waveform whose polarity is inverted each time timer z primary or timer z secondary underflows. (see table 1.14.11) a counting starts by counting the value set in the timer z primary. figure 1.14.26 shows timer y, z mode register and timer y, z waveform output control register in this mode. the timer z operates in the same way as the timer y in this mode. see figure 1.14.19 shown the timer y operating example in programmable waveform generation mode. item specification count source f 1 , f 8 , timer y underflow, f c32 count operation ? down count ? when the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting. ? when a counting stops, the timer reloads the content of the reload register before it stops. divide ratio fi/(n+1)/((m+1)+(l+1)) n : set value of prescaler z, m: set value of timer z primary, l: set value of timer z secondary count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) (note 1) interrupt request generation timing when timer z underflows during secondary period tz out pin function pulse output (note 2) int0 pin function programmable i/o port, or external interrupt input pin read from timer count value can be read out by reading timer z primary register. same applies to prescaler z register. (note 3) write to timer when a value is written to timer z primary register, it is written to only reload register. same applies to timer z secondary register and prescaler z register. (note 4) select function ? output level latch select function the output level of an waveform being counted during primary and secondary periods is selectable. ? programmable waveform generation output switching function can select either programmable waveform or the value of port p3 1 register for output. (note 5) ? waveform extend function (note 6) the waveform output primary and secondary periods can each be extended 0.5 cycles of the count source frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+tzpum0+tzpum1) duty: (2x(m+1)+tzpum0)/((2x(m+1)+tzpum0)+(2x(l+1)+tzpum1)) m: set value of timer z primary, l: set value of timer z secondary tzpum0: timer z primary waveform extension control bit tzpum1: timer z secondary waveform extension control bit note 1: when the count is stopped, the timer z interrupt request flag becomes "1" and an interrupt may occur. thus, interrupts must be disabled before the count is stopped. furthermore, set the timer z interrupt request bit to "0" before starting counting again. note 2: when the counting stopped, the pin is the secondary period output level. note 3: even when counting the secondary period, read out the timer z primary register. note 4: the set value of timer z secondary register and waveform extension control bits as well as timer z primary register are made effective by writing a value to the timer z primary register. the written values are reflected to the waveform output from the next primary period after writing to the timer z primary register. note 5: the switching of output is synchronized with a timer z secondary underflow. note 6: when using the waveform extend function, the prescaler z register must be set to "00 16 ". when selecting timer y underflow and f 1 for the count source, the waveform extend function cannot be used. table 1.14.11. specifications of programmable waveform generating mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 87 figure 1.14.26. timer y, z mode register and timer y, z waveform output control register in programmable waveform generation mode timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 1 : programmable waveform generation mode tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is "0". timer y-related bit note 1: when selecting programmable waveform generation mode, output is set for port p3 1 regardless of the value of the direction register. note 2: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. a a aa aa a aa a aa a a aa aa a aa timer y-related bits a aa tzwc tzs 0 : stops counting 1 : starts counting timer z write control bit timer z operation mode bit b5 b4 set to "1" in programmable waveform generation mode a aa (note 2) 101 (note 1) timer z count start flag bit name function bit symbol timer y-related bits typum 1 typum 0 tzpum0 tyopl tzpum1 tzop l inoseg inostg int0 pin one-shot trigger polarity select bit timer z output level latch wr aa a aa a aa aa a a aa a aa a aa a aa a aa a timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y-related bit int0 pin one-shot trigger control bit invalid in programmable waveform generation mode 0 : no waveform extension 1 : waveform extension 0 : no waveform extension 1 : waveform extension 0 : outputs "h" for the period set by timer z primary and "l" for the period set by timer z secondary. "l" is outputted when the timer is stopped. 1 : outputs "l" for the period set by timer z primary and "h" for the period set by timer z secondary. "h" is outputted when the timer is stopped. (note) (note) note : when setting this bit to "1", the prescaler z register must be set to "00 16 ". invalid in programmable waveform generation mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 88 (3) programmable one-shot generation mode _______ in this mode, upon software command or external trigger input (input to the int0 pin), the microcom- puter outputs the one-shot pulse from the tz out pin. (see table 1.14.12) when a trigger occurs, the timer starts operating from the point only once for a given period equal to the set value of the timer z primary. timer z secondary is unused in this mode. figure 1.14.27 shows the timer y, z mode register and timer y, z waveform output control register in this mode. figure 1.14.28 shows the timer z operation example in this mode. item specification count source f 1 , f 8 , timer y underflow, f c32 count operation ? downcounts the set value of timer z primary ? when the timer underflows, it reloads the contents of reload register before stopping counting. ? when a counting stops, the timer reloads the contents of the reload register before it stops. divide ratio 1/(n+1)/(m+1) n : set value of prescaler z, m: set value of timer z primary count start condition ? timer z one-shot start bit is set (=1) (note 1) _______ ? valid trigger is input to int0 pin (note 2) count stop condition ? when reloading is completed after count value was set to "00 16 " ? when count start flag is reset (=0) (note 3) ? timer z one-shot start bit is reset (=0) (note 3) interrupt request generation timing when count value becomes "00 16 " tz out pin function pulse output _______ int0 pin function programmable i/o port, external interrupt input pin, or external trigger input pin read from timer count value can be read out by reading timer z primary register. same applies to prescaler z register. write to timer when a value is written to timer z primary register, it is written to only reload register. same applies to prescaler z register. (note 4) select function ? output level latch select function the output level of one-shot pulse waveform is selectable. _______ ? int0 pin one-shot trigger control function and polarity select function _______ the trigger input from the int0 pin can be set to valid or invalid. also, the valid trigger's polarity can be chosen to be the rising edge, falling edge, or rising and falling both edges. ? waveform extend function the one-shot pulse waveform can be extended 0.5 cycles of the count source (note 5) frequency when waveform extended: 2/(n+1)/(2x(m+1)+tzpum0) n: set value of prescaler z, m: set value of timer z primary tzpum0: timer z primary waveform extension control bit note 1: count start flag must have been set to "1". _______ _______ note 2: count start flag must have been set to "1", int0 input enable bit [int0en] to "1", and int0 one-shot trigger control bit to "1". note 3: when the count is stopped by writing 0 to the count start flag or timer z one-shot start bit, the timer z interrupt request flag becomes "1" and an interrupt may occur. thus, interrupts must be disabled before the count is stopped. furthermore, set the timer z interrupt request bit to "0" before starting counting again. note 4: each set value becomes effective by writing to the timer z primary register. and the set values are reflected collectively beginning with the next one-shot pulse after writing to the timer z primary. note 5: when using the waveform extend function, the prescaler z register must be set to "00 16 ". when selecting timer y underflow and f 1 for the count source, the waveform extend function cannot be used. table 1.14.12. specifications of programmable one-shot generating mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 89 figure 1.14.27. timer y, z mode register and timer y, z waveform output control register in programmable one-shot generation mode timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 1 0 : programmable one-shot generation mode tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is "0". timer y-related bit note 1: when selecting programmable one-shot generation mode, output is set for port p3 1 regardless of the value of the direction register. note 2: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. aa a aa aa a a aa a aa a aa a timer y-related bits aa a tzwc tzs 0 : stops counting 1 : starts counting timer z count start flag timer z operation mode bit b5 b4 1: set to "1" in programmable one-shot generation mode aa aa a a (note 2) 011 (note 1) bit name function bit symbol timer y-related bits typum1 typum0 tzpum0 tyopl tzpum1 tzopl inoseg inostg int0 pin one-shot trigger polarity select bit timer z output level latch wr a a a a a a a a a a a a a a a a a a a a a a timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y-related bit int0 pin one-shot trigger control bit 0 : no waveform extension 1 : waveform extension invalid in programmable one-shot generation mode 0 : outputs "h" level one-shot pulse. "l" is outputted when the timer is stopped. 1 : outputs "l" level one-shot pulse "h" is outputted when the timer is stopped. (note 1) 0 : int0 pin one-shot trigger invalid 1 : int0 pin one-shot trigger valid 0 : edge trigger at falling edge 1 : edge trigger at rising edge (note 2) (note 3) note 1: when setting this bit to "1", the prescaler z register must be set to "00 16 ". note 2: this bit is valid only when int0 input polarity select bit (bit 1 at address 0096 16 ) is "0" (one-edge). note 3: when changing this bit to "1", set the int0 input filter select bit (bits 0, 1 of address 1e 16 ).
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 90 figure 1.14.28. operation example in programmable one-shot generation mode conditions: timer z primary=03 16 , timer z primary waveform extended, timer z output level latch [tzopl]="0", int0 one-shot trigger is valid at rising edge count start flag the contents of timer z tz out pin output 1 0 timer z interrupt request bit h l 1 0 1 0 f pz timer z output level latch initialized to "l" primary waveform extended aa aa a a 02 16 03 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 set to "1" by software set to "1" by software count start one-shot start bit 1 0 int0 pin input 1 0 timer z primary reload timer z primary reload count start cleared to "0" when counting completed set to "1" by int0 pin input trigger cleared to 0 when interrupt request is accepted, or cleared by software cleared to "0" by software primary waveform extended waveform output ends waveform output starts waveform output starts waveform output ends
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 91 (4) programmable wait one-shot generation mode _______ in this mode, upon software command or external trigger input (input to the int0 pin), the microcom- puter outputs the one-shot pulse from the tz out pin after waiting for a given length of time. (see table 1.14.13) when a trigger occurs, from this point, the timer starts outputting pulses only once for a given length of time equal to the timer z primary set value after waiting for a given length of time equal to the timer z primary set value. figure 1.14.29 shows the timer y, z mode register and timer y, z waveform output control register in this mode. figure 1.14.30 shows the timer z operation example in this mode. item specification count source f 1 , f 8 , timer y underflow, f c32 count operation ? downcounts the set value of timer z primary ? when timer z primary underflows, the contents of timer z secondary is reloaded be- fore continuing counting. ? when timer z secondary underflows, the contents of timer z primary is reloaded be- fore stopping counting. ? when a counting stops, the timer reloads the contents of the reload register before it stops. wait time fi x (n+1) x (m+1), n : set value of prescaler z, m: set value of timer z primary one-shot pulse output time fi x (n+1) x (l+1), n : set value of prescaler z, l: set value of timer z secondary count start condition ? timer z one-shot start bit is set (=1) (note 1) _______ ? valid trigger is input to int0 pin (note 2) count stop condition ? when reloading is completed after count value at counting timer z secondary was set to "00 16 " ? when count start flag is reset (=0) (note 3) ? timer z one-shot start bit is reset (=0) (note 3) interrupt request generation timing when count value at counting timer z secondary becomes "00 16 " tz out pin function pulse output _______ int0 pin function programmable i/o port, external interrupt input pin, or external trigger input pin read from timer count value can be read out by reading timer z primary register. same applies to prescaler z register. write to timer when a value is written to timer z primary register, it is written to only reload register. same applies to prescaler z register. (note 4) select function ? output level latch select function the output level of one-shot pulse waveform is selectable. _______ ? int0 pin one-shot trigger control function and polarity select function _____ the trigger input from the int0 pin can be set to valid or invalid. also, the valid trigger's polarity is selectable: rising edge, falling edge, or rising and falling both edges. ? waveform extend function waiting time and one-shot pulse waveform can each be extended 0.5 cycles of the count source (note 5) waiting time when waveform extended: fi x (n+1) x (2x(m+1)+tzpum0)/2 one-shot pulse output time when waveform extended: fi x (n+1) x (2x(l+1)+tzpum1)/2 n: set value of prescaler z, m: set value of timer z primary, l: set value of timer z secondary tzpum0: timer z primary waveform extension control bit, tzpum1: timer z secondary waveform extension control bit note 1: count start flag must have been set to "1". _______ _______ note 2: count start flag must have been set to "1", int0 input enable bit [int0en] to "1", and int0 one-shot trigger control bit to "1". note 3: when the count is stopped by writing 0 to the count start flag or timer z one-shot start bit, the timer z interrupt request flag becomes "1" and an interrupt may occur. thus, interrupts must be disabled before the count is stopped. furthermore, set the timer z interrupt request bit to "0" before starting counting again. note 4: each set value becomes effective by writing to the timer z primary register. and the set values are reflected collectively beginning with the next one-shot pulse after writing to the timer z primary. note 5: when using the waveform extend function, the prescaler z register must be set to "00 16 ". when selecting timer y underflow and f 1 for the count source, the waveform extend function cannot be used. table 1.14.13. specifications of programmable wait one-shot generating mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 92 figure 1.14.29. timer y, z mode register and timer y, z waveform output control register in programmable wait one-shot generation mode timer y, z mode register symbol address when reset tyzmr 0080 16 000000x0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 1 1 : programmable wait one-shot generation mode tzmod1 tys tywc tymod0 tzmod0 nothing is assigned. when write, set "0". when read, the content is "0". timer y-related bit note 1: when selecting programmable wait one-shot generation mode, output is set for port p3 1 regardless of the value of the direction register. note 2: when this bit is cleared to "0", the timer reloads the content of the reload register before it stops. read out the count value before you stop the timer. aa a aa aa a a aa a aa a aa a timer y-related bits aa a tzwc tzs 0 : stops counting 1 : starts counting timer z count start flag timer z operation mode bit b5 b4 1: set to "1" in programmable wait one-shot generation mode aa aa a a (note 2) 111 (note 1) bit name function bit symbol timer y-related bits typum1 typum0 tzpum0 tyopl tzpum1 tzopl inoseg inostg int0 pin one-shot trigger polarity select bit timer z output level latch wr a aa a aa a aa a aa a aa a aa a aa a aa timer y, z waveform output control register symbol address when reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y-related bit int0 pin one-shot trigger control bit 0 : no waveform extension 1 : waveform extension 0 : outputs "h" level one-shot pulse. "l" is outputted when the timer is stopped. 1 : outputs "l" level one-shot pulse "h" is outputted when the timer is stopped. (note 1) 0 : int0 pin one-shot trigger invalid 1 : int0 pin one-shot trigger valid 0 : edge trigger at falling edge 1 : edge trigger at rising edge (note 2) 0 : no waveform extension 1 : waveform extension ( note 1) (note 3) note 1: when setting this bit to "1", the prescaler z register must be set to "00 16 ". note 2: this bit is valid only when int0 input polarity select bit (bit 1 at address 0096 16 ) is "0" (one-edge). note 3: when changing this bit to "1", set the int0 input filter select bit (bits 0, 1 of address 1e 16 ).
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer z 93 figure 1.14.30. operation example in programmable wait one-shot generation mode conditions: timer z primary=03 16 , timer z primary waveform extended, timer z primary=04 16 , timer z secondary waveform not extended, timer z output level latch [tzopl]="0", int0 one-shot trigger is valid at rising edge initialized to "l" count start flag the contents of timer z tz out pin output 1 0 timer z interrupt request bit h l 1 0 1 0 f pz timer z output level latch one-shot start bit 1 0 int0 pin input 1 0 02 16 03 16 01 16 00 16 04 16 02 16 01 16 00 16 03 16 03 16 cleared to 0 when interrupt request is accepted, or cleared by software set to "1" by software set to "1" by software, or set to "1" by int0 pin input trigger cleared to "0" when counting completed timer z primary reload timer z secondary reload count start cleared to "0" by software waveform output starts waveform output ends wait starts note: the waveform output of one-shot pulse is completed after 0.5 clock (1 clock when primary waveform extended) of f pz from occurrence of timer z interrupt request. (note)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer c 94 figure 1.14.31. block diagram of timer c timer c timer c is a 16-bit free-running timer. figure 1.14.31 shows the block diagram of timer c. the timer c uses an edge input to tc in pin or the output of 512 f ring divisions as trigger to latch the timer count value and generates an interrupt request. the tc in input has a digital filter and this prevents an error caused by noise or so on from occurring. table 1.14.14 shows timer c specifications. figure 1.14.32 shows timer c-related registers. figure 1.14.33 shows an operation example of timer c and timer measurement register. item specification count source f 1 , f 8 , f 32 count operation ? up count ? transfer counter value to time measurement register at active edge of measurement pulse ? do not reset counter value even if active edge is detected count start condition ? time measurement control bit is set (=1) counter stop condition ? time measurement control bit is reset (=0) interrupt request generation timing ? when active edge of measurement pulse is input [tcin interrupt] ? when the time underflows [timer c interrupt] tcin pin function measurement pulse input count value reset timing when time measurement control bit is reset (=0) read from timer (note) ? count value can be read out by reading timer c. (note) ? count value at measurement pulse active edge input can be read out by reading time measurement register. write to timer cannot write to timer c and time measurement register select function ? measurement pulse active edge: selectable (rising edge/falling edge/both edges) ? measurement pulse: selectable (input from tc in pin/512 divisions of f ring ) ? digital filter sampling frequency: selectable (f 1 /f 8 /f 32 ) note: the timer c and the timer measurement register must be read in word-size. time measurement register (16) upper 8 bits lower 8 bits timer c counter (16) f 1 f 8 f 32 edge detection tcin 1/256 1/2 ring oscillation tcin interrupt timer c overflow interrupt time measurement input source switching bit "0" "1" timer c clock select bit reload signal digital filter f 1 f 8 f 32 digital filter clock select bit address 009d 16 address 009c 16 address 0090 16 address 0091 16 data bus upper 8 bits lower 8 bits table 1.14.14. specifications of timer c
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer c 95 symbol address when reset tc 0091 16 , 0090 16 indeterminate wr internal count source is counted function timer c a symbol address when reset tm 009c 16 , 009d 16 indeterminate wr when active edge of measurement pulse is input, the count value of timer c is stored function time measurement register a a b7 b0b7b0 (b15) (b8) b7 b0b7b0 (b15) (b8) note: when time measurement is disabled, the value is indeterminate. after enabling time measurement, the value is indeterminate until the first trigger is generated. (note) timer c control register 0 symbol address when reset tcc0 009a 16 0xx00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : inhibit tcc04 tcc02 tcc01 tcc00 tcc03 nothing is assigned. when write, set "0". when read, their contents are "0". time measurement control bit aa a aa aa a a timer c clock select bit 0 : time measurement disabled 1 : time measurement enabled aa a tcc07 b2 b1 time measurement input edge trigger bit time measurement input source switching bit aa aa a a 0 : tcin 1 : ring512 timer c control register 1 symbol address when reset tcc1 009b 16 xxxxxx11 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 tcc11 tcc10 nothing is assigned. when write, set "0". when read, their contents are "0". aa a 0 0 : rising edge 0 1 : falling edge 1 0 : both edges 1 1 : inhibit b4 b3 0 0 : cannot be used 0 1 : f1 1 0 : f8 1 1 : f32 b1 b0 digital filter clock select bit note 1: change this bit when time measurement is disabled. note 2: when using an external rc circuit for the main clock, f 1 cannot be selected for the timer c clock. note 3: set the ring oscillation stop bit (cm14) to 0 before setting this bit to 1. (note 1) (note 1) (note 1) (note 3) (note) note : input edge becomes active when the same value from tc in pin is sampled three times in succession. (note 2) figure 1.14.32. timer c-related register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer timer c 96 counter contents (hex) time measurement control bit measurement pulse (tcin pin input) time measurement register ffff 16 0000 16 conditions: time measurement input edge trigger is set for falling egde (tcc03="1", tcc04="0") count start timer c interrupt request bit h l 1 0 cleared to 0 when interrupt request is accepted, or cleared by software cleared to "0" by software set to "1" by software overflow measurement value 2 indeterminate cleared to 0 when interrupt request is accepted, or cleared by software tcin interrupt request bit measurement value 1 transmit timing from timer c counter to time measurement register measurement value 1 measurement value 2 measurement value 3 indeterminate transmit (measurement value 3) transmit (measurement value 2) transmit (measurement value 1) time measure- ment value 3 1 0 1 0 the delay caused by digital filter figure 1.14.33. operation example of timer c and time measurement register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 97 figure 1.15.1. block diagram of uarti (i = 0, 1) serial i/o serial i/o is configured as two channels: uart0 and uart1. uart0 and uart1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 1.15.1 shows the block diagram of uarti (i=0,1). figure 1.15.2 shows the block diagram of the transmit/receive unit. uart0 has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/ o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 00a0 16 and 00a8 16 ) determine whether uart0 is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0 and uart1 have almost the same functions. figures 1.15.3 through 1.15.5 show the registers related to uarti. bit rate generator clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clock source selection internal external bit rate generator receive clock transmit clock clock source selection n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) clock output pin select switch rxd 0 1 / (n 0 +1) 1/16 1/16 1/2 clk 0 f 1 (address 00a1 16 ) txd 0 rxd 1 1 / (n 1 +1) 1/16 1/16 1/2 clk 1 (address 00a9 16 ) txd 1 (uart1) (uart0) clks 1 reception control circuit transmission control circuit transmit/ receive unit clk polarity reversing circuit transmit/ receive unit reception control circuit transmission control circuit clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) internal external clk polarity reversing circuit f 32 f 8 f 1 f 32 f 8 f c f c
serial i/o under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 98 sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 data bus high-order bits figure 1.15.2. block diagram of transmit/receive unit
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 99 b7 uarti bit rate generator b0 symbol address when reset u0brg 00a1 16 indeterminate u1brg 00a9 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set wr a a b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data (note) nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. symbol address when reset u0tb 00a3 16 , 00a2 16 indeterminate u1tb 00ab 16 , 00aa 16 indeterminate wr a (b15) symbol address when reset u0rb 00a7 16 , 00a6 16 indeterminate u1rb 00af 16 , 00ae 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note: bits 15 through 12 are set to 0 when the serial i/o mode select bits (bit 2 to 0 at addresses 00a0 16 and 00a8 16 ) are set to 000 2 or receive enable bit to 0. (bit 15 is set to 0 when bits 14 to 12 all are set to 0.) bits 14 and 13 are also set to 0 when the lower byte of the uarti receive buffer register (addresses 00a6 16 , and 00ae 16 ) is read out or when this register is read out in word-size. when reading data from the uarti receive buffer, data should be read high-byte first then low-byte using byte- size. invalid invalid invalid oer fer per sum overrun error flag (note) framing error flag (note) parity error flag (note) error sum flag (note) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. receive data wr receive data a a a a a a note: when transfer data length is 9-bit long, write high-byte first then low-byte with byte- size. figure 1.15.3. serial i/o-related registers (1)
serial i/o under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 100 uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 00a0 16 , 00a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol wr must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = 1 0 : odd parity 1 : even parity invalid invalid function (during uart mode) function (during clock synchronous serial i/o mode) aa a aa a aa aa a a aa a aa a aa a aa aa a a aa aa a a uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 00a4 16 , 00ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) wr function (note) (during clock synchronous serial i/o mode) txept clk1 clk0 nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : fc is selected b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : fc is selected b1 b0 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol must always be 0 o aa aa a a aa aa a a aa aa aa a aa a aa a must set to "0". (note) note: set the corresponding port direction register to 0. 0 aa a reserved bit nothing is assigned. in an attempt to write to this bit, write "0". the value, if read, turns out to be "0". reserved bit must always be set to 0 figure 1.15.4. serial i/o-related registers (2)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 101 uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 00a5 16 , 00ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function (during uart mode) function (note 1) (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit (note) receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. in an attempt to write to these bits, write "0". the value, if read, turns out to be "0". note 1: when using multiple pins to output the transfer clock, the following requirements must be met: ? uart1 internal/external clock select bit (bit 3 at address 00a0 16 ) = 0. note 2: for p3 7 , select "0" for data receive, and "1" for data transfer. and set the direction register of port p3 7 to input ("0") when receiving. uart transmit/receive control register 2 symbol address when reset ucon 00b0 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk0 only) 1 : transfer clock output from multiple pins function selected 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) fixed to 0 u0irs u1irs u0rrm clk/clks select bit 1 (note 1) valid when bit 5 = 1 0 : clock output to clk1 1 : clock output to clks1 note : as for the uart1, set the rxd 1 input port select bit before setting this bit to reception enabled. wr aa a aa aa aa a aa aa wr aa a aa aa a a aa aa a a aa aa a a aa a aa a invalid invalid 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) nothing is assigned. in an attempt to write to these bits, write "0". the value, if read, turns out to be "0". uart1 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable u1rrm invalid rxd1en 0 : p3 7 1 : p3 5 rxd 1 input port select bit 0 : p3 7 1 : p3 5 aa a (note 2) figure 1.15.5. serial i/o-related registers (3)
serial i/o under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 102 specification ? transfer data length: 8 bits ? when internal clock is selected (bit 3 at address 00a0 16 ,00a8 16 = 0) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 , fc ? when external clock is selected (bit 3 at address 00a0 16 ,00a8 16 = 1) : input from clki pin ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at address 00a5 16 ,00ad 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 00a5 16 ,00ad 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at address 00a4 16 ,00ac 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at address 00a4 16 ,00ac 16 ) = 1: clki input level = l ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at address 00a5 16 ,00ad 16 ) = 1 _ transmit enable bit (bit 0 at address 00a5 16 ,00ad 16 ) = 1 _ transmit buffer empty flag (bit 1 at address 00a5 16 ,00ad 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at address 00a4 16 ,00ac 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at address 00a4 16 ,00ac 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bit 0 and bit 1 at address 00b0 16 ) = 0: inter- rupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bit 0 and bit 1 at address 00b0 16 ) = 1: inter- rupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti re- ceive buffer register is completed ? overrun error (note 2) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection uart1 transfer clock can be chosen by software to be output from one of the two pins set ? rxd 1 input pin selection uart1 rxd 1 can be chosen by software to be input to one of the two pins set clock synchronous serial i/o mode item transfer data format transfer clock transmission start condition reception start conditio interrupt request generation timing error detection select function table 1.15.1. specifications of clock synchronous serial i/o mode (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. (see table 1.15.1.) figure 1.15.6 shows the uarti transmit/receive mode register. note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit does not change.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 103 clock synchronous serial i/o mode symbol address when reset uimr (i=0,1) 0 0a0 16 , 00a8 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (note) bit name functionbit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be 0 in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode a aa a a aa aa a aa a aa a aa a aa a aa a a aa aa note : set the corresponding port direction register to 0. (when transfer clock output from multiple pins is not selected) pin name method of selection txd 0 (p1 4 ) function serial data output serial data input transfer clock output transfer clock input rxd 0 (p1 5 ) clki (p1 6 , p3 6 ) internal/external clock select bit (bit 3 at addresses 00a0 16 and 00a8 16 ) = 0 internal/external clock select bit (bit 3 at address 00a0 16 and 00a8 16 ) = 1 ports p1 6 and p3 6 direction register (bit 6 at address 00e3 16 and 00e7 16 ) = 0 txd 1 (p3 7 ) rxd 1 (p3 5 ) rxd 1 (p3 7 ) clki (p1 6 , p3 6 ) port p1 5 direction register (bit 5 at address 00e1 16 )= 0 port p3 5 direction register (bit 5 at address 00e7 16 )= 0 rxd 1 input pin select bit (bit 6 at address 00b0 16 )= 1 port p3 7 direction register (bit 7 at address 00e7 16 )= 0 rxd 1 input pin select bit (bit 6 at address 00b0 16 )= 0 rxd 1 input pin select bit (bit 6 at address 00b0 16 )= 1 port p1 4 cannot be used as an i/o port even when performing only serial data input but not serial data output) port p3 7 cannot be used as an i/o port even when performing only serial data input but not serial data output) port p1 5 can be used as an i/o port when performing only serial data output but not serial data input) port p3 5 can be used as an i/o port when performing only serial data output but not serial data input) when setting port p3 7 as rxd 1 , serial data output cannot be performed. port p3 5 can be used as an i/o port. remarks table 1.15.2. input/output pin functions in clock synchronous serial i/o mode table 1.15.2 lists the functions of the input/output pins during clock synchronous serial i/o mode. this table shows the pin functions when the transfer clock output from multiple pins is not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h. (if the n-channel open-drain is selected, this pin is in floating state.) figure 1.15.6. uarti transmit/receive mode register in clock synchronous serial i/o mode
serial i/o under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 104 ? example of transmit timing (when internal clock is selected) ? example of receive timing (when external clock is selected) clock synchronous serial i/o mode tc = t clk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 , fc) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) 0 1 0 1 0 1 the above timing applies to the following settings: ? internal clock is selected. ? clk polarity select bit = 0. ? transmit interrupt cause select bit = 0. transmit interrupt request bit (ir) 0 1 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) 0 1 0 1 0 1 receive enable bit (re) 0 1 receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ? external clock is selected. ? clk polarity select bit = 0. f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. meet the following conditions when the clki input level before data reception = h ? transmit enable bit 1 ? receive enable bit 1 ? dummy data write to uarti transmit buffer register shown in ( ) are bit symbols. cleared to 0 when interrupt request is accepted, or cleared by software tc t clk stopped pulsing because transfer enable bit = 0 data is set in uarti transmit buffer register transferred from uarti transmit buffer register to uarti transmit register cleared to 0 when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 figure 1.15.7. typical transmit/receive timings in clock synchronous serial i/o mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 105 lsb first ? when transfer format select bit = 0 d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ? when transfer format select bit = 1 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = 0. clock synchronous serial i/o mode ? when clk polarity select bit = 1 note 2: the clki pin level when not transferring data is l. d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ? when clk polarity select bit = 0 note 1: the clki pin level when not transferring data is h. d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i (a) polarity select function as shown in figure 1.15.8, the clk polarity select bit (bit 6 at addresses 00a4 16 and 00ac 16 ) allows selection of the polarity of the transfer clock. (b) lsb first/msb first select function as shown in figure 1.15.9, when the transfer format select bit (bit 7 at addresses 00a4 16 and 00ac 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 1.15.8. polarity of transfer clock figure 1.15.9. transfer format
serial i/o under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 106 clock synchronous serial i/o mode microcomputer t x d 1 (p3 7 ) clks (p3 4 ) clk 1 (p3 6 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode. (c) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 00b0 16 ). (see figure 1.15.10.) the multiple pins function is valid only when the internal clock is selected for uart1. (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 00b0 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) rxd 1 input pin selection function (uart1) this function allows the setting two rxd 1 input pins and choosing one of the two to input serial data by using the rxd 1 input pin select bit (bits 6 at address 00b0 16 ). when selecting "1" (p3 5 ) for rxd 1 input pin select bit, p3 7 functions as txd 1 output pin. when select- ing "0" (p3 7 ), serial data output cannot be performed. however, p3 5 can be used as an input/output port. figure 1.15.10. the transfer clock output from the multiple pins function usage
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 107 (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. (see table 1.15.3.) figure 1.15.11 shows the uarti transmit/receive mode register. clock asynchronous serial i/o (uart) mode transfer data format transfer clock transmission start condition reception start condi- tion interrupt request gen- eration timing error detection select function item specification ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected ? when internal clock is selected (bit 3 at addresses 00a0 16 , 00a8 16 = 0) : fi/ 16 (n+1) (note 1) fi = f 1 , f 8 , f 32 , f c ? when external clock is selected (bit 3 at addresses 00a0 16 =1) : f ext /16(n+1) (note 1) (note 2) ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 00a5 16 , 00ad 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 00a5 16 , 00ad 16 ) = 0 ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 00a5 16 , 00ad 16 ) = 1 - start bit detection ? when transmitting - transmit interrupt cause select bits (bits 0,1 at address 00b0 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 00b0 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered ? rxd 1 input pin selection uart1 rxd 1 can be chosen by software to be input to one of the two pins set table 1.15.3. specifications of uart mode note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit does not change.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 108 figure 1.15.11. uarti transmit/receive mode register in uart mode clock asynchronous serial i/o (uart) mode symbol address when reset uimr(i=0,1) 00a0 16 , 00a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye 0 : internal clock 1 : external clock (note 1) bit name functionbit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = 1 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit a a a a a a a a a a a a a a a a a a a a note : set the corresponding port direction register to 0. reserved bit m ust always be set to 0 pin name method of selection txd 0 (p1 4 ) function serial data output serial data input transfer clock input rxd 0 (p1 5 ) internal/external clock select bit (bit 3 at address 00a0 16 and 00a8 16 ) = 1 ports p1 6 and p3 6 direction register (bit 6 at address 00e3 16 and 00e7 16 ) = 0 txd 1 (p3 7 ) rxd 1 (p3 5 ) rxd 1 (p3 7 ) clki (p1 6 , p3 6 ) port p1 5 direction register (bit 5 at address 00e1 16 )= 0 port p3 5 direction register (bit 5 at address 00e7 16 )= 0 rxd 1 input pin select bit (bit 6 at address 00b0 16 )= 1 port p3 7 direction register (bit 7 at address 00e7 16 )= 0 rxd 1 input pin select bit (bit 6 at address 00b0 16 )= 0 rxd 1 input pin select bit (bit 6 at address 00b0 16 )= 1 port p1 4 cannot be used as an i/o port even when performing only serial data input but not serial data output) port p3 7 cannot be used as an i/o port even when performing only serial data input but not serial data output) port p1 5 can be used as an i/o port when performing only serial data output but not serial data input) port p3 5 can be used as an i/o port when performing only serial data output but not serial data input) when setting port p3 7 as rxd 1 , serial data output cannot be performed. port p3 5 can be used as an i/o port. remarks ports p1 6 and p3 6 can be used as an i/o port when not performing transfer clock input. in this case, set the internal/external clock select bit to "0". table 1.15.4 lists the functions of the input/output pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n- channel open-drain is selected, this pin is in floating state.) table 1.15.4. input/output pin functions in uart mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 109 ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) clock asynchronous serial i/o (uart) mode transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi the above timing applies to the following settings : ? parity is enabled. ? one stop bit. ? transmit interrupt cause select bit = 1. 1 0 1 0 1 tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 , f c ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) 0 1 cleared to 0 when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) 0 1 0 1 0 1 the above timing applies to the following settings : ? parity is disabled. ? two stop bits. ? transmit interrupt cause select bit = 0. transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 , f c ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) 0 1 shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp stop bit transferred from uarti transmit buffer register to uarti transmit register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 st stopped pulsing because transmit enable bit = 0 start bit data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. 0 sp cleared to 0 when interrupt request is accepted, or cleared by software figure 1.15.12. typical transmit timings in uart mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer serial i/o 110 ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) clock asynchronous serial i/o (uart) mode d 0 start bit sampled l brgi count source receive enable bit rxdi transfer clock receive complete flag stop bit 1 0 0 1 the above timing applies to the following settings : ?parity is disabled. ?one stop bit. receive interrupt request bit 0 1 reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to 0 when interrupt request is accepted, or cleared by software transferred from uarti receive register to uarti receive buffer register receive data taken in (a) rxd 1 input pin selection function (uart1) this function allows the setting two rxd 1 input pins and choosing one of the two to input serial data by using the rxd 1 input pin select bit (bits 6 at address 00b0 16 ). when selecting "1" (p3 5 ) for rxd 1 input pin select bit, p3 7 functions as txd 1 output pin. when select- ing "0" (p3 7 ), serial data output cannot be performed. however, p3 5 can be used as an input/output port. figure 1.15.13. typical receive timing in uart mode
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer a-d converter 111 a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p0 0 to p0 7 , p1 0 to p1 3 , p4 0 and p4 1 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 00d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the refer- ence voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after connecting to v ref . the result of a-d conversion is stored in the a-d registers. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 1.16.1 shows the performance of the a-d converter. figure 1.16.1 shows the block diagram of the a- d converter, and figures 1.16.2 and 1.16.3 show the a-d converter-related registers. table 1.16.1. performance of a-d converter item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to v cc operating clock ad (note 2) v cc = 5v f ad , divide-by-2 of f ad , divide-by-4 of f ad , f ad =f(x in ) v cc = 3v divide-by-2 of f ad , divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? with sample and hold function (10-bit resolution) an 0 to an 11 input : 3lsb anex 0 and anex 1 input (including mode in which external operation amp is connected) : 7lsb v cc = 3v ? without sample and hold function (8-bit resolution) 2lsb operating modes one-shot mode and repeat mode (note 3) analog input pins 12 pins (an 0 to an 11 ) + 2 pins (anex 0 to anex 1 ) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 conversion speed per pin ? without sample and hold function 8-bit resolution: 49 ad cycles , 10-bit resolution: 59 ad cycles ? with sample and hold function 8-bit resolution: 28 ad cycles , 10-bit resolution: 33 ad cycles note 1: does not depend on use of sample and hold function. note 2: divide f ad if (x in ) exceeds 10mhz, and make ad equal to or lower than 10mhz. also if vcc is less than 4.2v or an external rc circuit is used for the main clock, divide f ad and make ad equal to or lower than f ad /2. without sample and hold function, set the ad frequency to 250khz min. with the sample and hold function, set the ad frequency to 1mhz min. note 3: in repeat mode, only 8-bit mode can be used.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer a-d converter 112 1/2 f ad 1/2 f ad a-d conversion rate selection (00c1 16 , 00c0 16 ) cks1=1 cks0=0 a-d register 0(16) resistor ladder successive conversion register a-d control register 0 (address 00d6 16 ) a-d control register 1 (address 00d7 16 ) v ref v in data bus low-order v ref vcut=0 v ss vcut=1 cks0=1 cks1=0 decoder comparator addresses ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 opa1, opa0=0, 0 port p0 group p0 7 /an 0 p0 6 /an 1 p0 5 /an 2 p0 4 /an 3 p0 2 /an 5 p0 1 /an 6 p0 0 /an 7 p0 3 /an 4 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 port p1 group p1 0 /an 8 p1 2 /an 10 p1 3 /an 11 p1 1 /an 9 opa1=1 opa1,opa0=1,1 p4 0 /anex0 p4 1 /anex1 opa1,opa0=0,1 opa0=1 adgsel0=1 adgsel0=0 figure 1.16.1. block diagram of a-d converter
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer a-d converter 113 a-d control register 0 (note 1) symbol address when reset adcon0 00d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 , an 8 is selected 1 0 1 : an 5 , an 9 is selected 1 1 0 : an 6 , an 10 is selected 1 1 1 : an 7 , an 11 is selected ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 : one-shot mode 1 : repeat mode md0 adgsel0 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 wr a-d control register 1 (note 1) symbol address when reset adcon1 00d7 16 00 16 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 opa0 opa1 external op-amp connection mode bit wr b2 b1 b0 0 0 : anex 0 and anex 1 are not used 0 1 : anex 0 input is a-d converted 1 0 : anex 1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. note 3: an 4 to an 7 and an 8 to an 11 are selected by the a-d input group select bit. note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: in repeat mode, only 8-bit mode can be used. note 3: when f(x in ) is over 10 mhz, the ad frequency must be under 10 mhz by dividing. a a a a a a a a a a a a a a a a a a bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 0 : vref not connected 1 : vref connected frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 aa a aa aa a a aa aa a a aa aa a a a aa 0 set this bit to 0. 0 set this bit to 0. when read, their values are 0. (note 2) (note 2, 3) a-d input group select bit 0 : port p0 group is selected 1 : port p1 group is selected aa a 00 (note 2) (note 3) figure 1.16.2. a-d converter-related registers (1)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer a-d converter 114 a-d control register 2 (note) symbol address when reset adcon2 00d4 16 xxxx0000 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a a a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. a-d register symbol address when reset ad 00c0 16 indeterminate 00c1 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. during 8-bit mode the value, if read, turns out to be indeterminate. a a a a smp 000 a a a a reserved bit a lways set to 0 figure 1.16.3. a-d converter-related registers (2)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer a-d converter 115 (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. (see table 1.16.2.) figure 1.16.4 shows the a-d control register in one-shot mode. a-d control register 0 (note 1) symbol address when reset adcon0 00d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 , an 8 is selected 1 0 1 : an 5 , an 9 is selected 1 1 0 : an 6 , an 10 is selected 1 1 1 : an 7 , an 11 is selected ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 : one-shot mode md0 adgsel0 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 wr a-d control register 1 (note 1) symbol address when reset adcon1 00d7 16 00 16 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 opa0 opa1 external op-amp connection mode bit wr b2 b1 b0 0 0 : anex 0 and anex 1 are not used 0 1 : anex 0 input is a-d converted 1 0 : anex 1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. note 3: an 4 to an 7 and an 8 to an 11 are selected by the a-d input group select bit. note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when f(x in ) is over 10 mhz, the ad frequency must be under 10 mhz by dividing. a a a a a a a a a a a a a a a a a a a a a a bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 1 : vref connected frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a a a a a a a a a a 0 set this bit to 0. 0 set this bit to 0. when read, their values are 0. (note 2) (note 2, 3) a-d input group select bit 0 : port p0 group is selected 1 : port p1 group is selected a a a a 00 (note 2) 0 1 figure 1.16.4. a-d conversion register in one-shot mode item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 11 , as selected reading of result of a-d converter read a-d register table 1.16.2. one-shot mode specifications
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer a-d converter 116 (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. (see table 1.16.3.) figure 1.16.5 shows the a-d control register in repeat mode. a-d control register 0 (note 1) symbol address when reset adcon0 00d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 , an 8 is selected 1 0 1 : an 5 , an 9 is selected 1 1 0 : an 6 , an 10 is selected 1 1 1 : an 7 , an 11 is selected ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 : repeat mode md0 adgsel0 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 wr a-d control register 1 (note 1) symbol address when reset adcon1 00d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 opa0 opa1 external op-amp connection mode bit wr b2 b1 b0 0 0 : anex 0 and anex 1 are not used 0 1 : anex 0 input is a-d converted 1 0 : anex 1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. note 3: an 4 to an 7 and an 8 to an 11 are selected by the a-d input group select bit. note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: in repeat mode, only 8-bit mode can be used. note 3: when f(x in ) is over 10 mhz, the ad frequency must be under 10 mhz by dividing. a a a a a a a a a a a a a a a a a a a a a a bits 8/10-bit mode select bit 0 : 8-bit mode vcut vref connect bit 1 : vref connected frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a a a a a a a a a a a a a a 0 set this bit to 0. 0 set this bit to 0. when read, their values are 0. (note 2) (note 2, 3) a-d input group select bit 0 : port p0 group is selected 1 : port p1 group is selected a a 00 (note 2) (note 3) 10 1 figure 1.16.5. a-d conversion register in repeat mode item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 11 , as selected (note) reading of result of a-d converter read a-d register (at any time) note : an 4 to an 7 can be used in the same way as for an 8 to an 11 . table 1.16.3. repeat mode specifications
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer a-d converter 117 external op-amp analog input an 0 an 7 an 1 an 2 an 3 an 4 an 5 an 6 anex 1 anex 0 resistance ladder successive conversion register comparator an 11 an 8 an 9 an 10 adgsel0=1 adgsel0=0 figure 1.16.6. example of external op-amp connection mode sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 00d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 ? ad cycle is achieved with 8-bit resolution and 33 ? ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used. extended analog input pins in one-shot mode and repeat mode, the input via the extended analog input pins anex 0 and anex 1 can also be converted from analog to digital. when bit 6 of the a-d control register 1 (address 00d7 16 ) is 1 and bit 7 is 0, input via anex 0 is converted from analog to digital. when bit 6 of the a-d control register 1 (address 00d7 16 ) is 0 and bit 7 is 1, input via anex 1 is converted from analog to digital. external operation amp connection mode in this mode, multiple external analog inputs via the extended analog input pins, anex 0 and anex 1 , can be amplified together by just one operation amp and used as the input for a-d conversion. when bit 6 of the a-d control register 1 (address 00d7 16 ) is 1 and bit 7 is 1, input via an 0 to an 11 is output from anex 0 . the input from anex 1 is converted from analog to digital and the result stored in the a-d register. the speed of a-d conversion depends on the response of the external operation amp. do not connect the anex 0 and anex 1 pins directly. figure 1.16.6 is an example of how to connect the pins in external operation amp mode.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer d-a converter 118 d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains one independent d-a converter of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bit 0 (d-a output enable bit) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. when d-a output is set for enabled, the corre- sponding port is inhibited to be pulled up. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 1.17.1 lists the performance of the d-a converter. figure 1.17.1 shows the block diagram of the d-a converter, figure 1.17.2 shows the d-a control register and figure 1.17.3 shows d-a converter equivalent circuit. d-a register (8) r-2r resistance ladder (address 00d8 16 ) d-a output enable bit a aaaaa aaaaa p3 4 / clks 1 / da figure 1.17.1. block diagram of d-a converter table 1.17.1. performance of d-a converter item performance conversion method r-2r method resolution 8 bits analog output pin 1 channel
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer d-a converter 119 v ref v ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r d-a output enable bit da "1" "0" msb lsb d-a register 0 "0" "1" note 1: in the above figure, the d-a register value is "2a 16 ". note 2: to save power when not using the d-a converter, set the d-a output enable bit to "0" and the d-a register to "00 16 ", and prevent current flowing to the r-2r resistance. d-a control register symbol address when reset dacon 00dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a output enable bit dae bit symbol bit name function r w 0 : output disabled 1 : output enabled must always set to 0 reserved bit nothing is assigned. when write, set "0". when read, the value of these bits is "0". d-a register symbol address when reset da 00d8 16 indeterminate wr b7 b0 function r w output value of d-a conversion a aa a aa nothing is assigned. when write, set "0". when read, the value of this bit is "0". 0 figure 1.17.2. d-a control register figure 1.17.3. d-a converter equivalent circuit
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 120 programmable i/o ports there are 34 programmable i/o ports: p0 to p4 (when M30102). each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. the port p1 allows the drive capacity of its n-channel output transistor to be set as necessary. the port p1 can be used as led drive port if the drive capacity is set to high. figures 1.18.1 to 1.18.4 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 1.18.5 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. (2) port registers figure 1.18.6 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 1.18.7 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. (4) port p1 drive capacity control register figure 1.18.7 shows a structure of the port p1 drive capacity control register. this register is used to control the drive capacity of the port p1's n-channel output transistor. each bit in this register corresponds one for one to the port pins.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 121 figure 1.18.1. programmable i/o ports (1) p0 0 to p0 7 , p4 0 , p4 1 data bus pull-up selection a-d input direction register port latch p1 0 to p1 3 input to respective peripheral functions p1 x driving capacity direction register port latch pull-up selection data bus a-d input p1 4 data bus pull-up selection output "1" p1 4 driving capacity port latch direction register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 122 figure 1.18.2. programmable i/o ports (2) p1 6 , p1 7 input to respective peripheral functions pull-up selection data bus direction register port latch p1 x driving capacity output "1" p2 0 , p2 1 data bus pull-up selection direction register port latch p1 5 input to respective peripheral functions pull-up selection p1 5 driving capacity data bus port latch direction register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 123 figure 1.18.3. programmable i/o ports (3) p3 0 , p3 1 , p3 2 output "1" port latch pull-up selection data bus direction register p3 4 data bus output analog input d-a output enable "1" port latch pull-up selection d-a output enable direction register p3 7 , p3 6 output data bus pull-up selection "1" input to respective peripheral functions port latch direction register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 124 figure 1.18.4. programmable i/o ports (4) note : symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. p4 7 (note) fc rf pull-up selection data bus port latch p4 6 rd pull-up selection data bus direction register port latch output "1" (note) direction register p4 5 port latch pull-up selection data bus input to respective peripheral functions digital filter direction register p3 3 , p3 5 , p4 2 to p4 4 port latch pull-up selection data bus input to respective peripheral functions direction register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 125 port pi register (note) bit name functionbit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : l level data 1 : h level data a a aa aa a aa a aa a aa a aa a a aa aa a a aa aa a aa a aa symbol address when reset pi (i = 0 to 4) 00e0 16 , 00e1 16 , 00e4 16 , indeterminate 00e5 16 , 00e8 16 indeterminate note : nothing is assigned in bit 2 to bit 7 of port p2 register. when write, set 0. when read, their contents are 0. figure 1.18.6. port register port pi direction register (notes 1, 2) symbol address when reset pdi (i = 0 to 4) 00e2 16 , 00e3 16 , 00e6 16 , 00 16 00e7 16 , 00ea 16 00 16 bit name functionbit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note 1: set bit 2 of protect register (address 000a 16 ) to 1 before rewriting to the port p0 direction register. note 2: nothing is assigned in bit 2 to bit 7 of port p2 direction register. when write, set 0. when read, their contents are 0. a a a a a a a a a a a a a a a a a a a a a a figure 1.18.5. direction register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 126 pull-up control register 0 symbol address when reset pur0 00fc 16 00x00000 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high a aa a a aa aa a aa a a aa aa a aa a a aa aa a a aa aa port p1 drive capacity control register symbol address when reset drr 00fe 16 00 16 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 drr0 port p1 0 drive capacuty drr1 port p1 1 drive capacuty drr2 port p1 2 drive capacuty drr3 port p1 3 drive capacuty drr4 port p1 4 drive capacuty drr5 port p1 5 drive capacuty drr6 port p1 6 drive capacuty drr7 port p1 7 drive capacuty set p1 n-channel output transistor drive capacity 0 : low 1 : high a aa a a aa aa a aa a a aa aa a aa a aa a a aa aa a aa pu04 p2 0 , p2 1 pull-up pull-up control register 1 symbol address when reset pur1 00fd 16 xxxxxx 00 2 bit name function bit symbol wr b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu11 p4 4 to p4 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high a aa a aa a aa nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. figure 1.18.7. pull-up control register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer programmable i/o port 127 pin name connection ports p0 to p4 x out (note 2) v ref after setting for input mode, connect every pin to v ss (pull-down) via a resistor; or after setting for output mode, leave these pins open. open connect to v ss note 1: connect unused pins as described above. if connected otherwise, power supply current may increase due to flow-through current on schmitt circuit in the port. note 2: with external clock input to x in pin, or the main clock oscillation circuit isn't used. note 3: when the main clock oscillation circuit isn't used, connect x in pin to v cc (pull-up), leave x out pin open.or set main clock stop bit (bit 5 at address 0006 16 ) to "1"(stop). (note 1) x in (note 3) connect to v cc (pull-up) via a resistor table 1.18.1. example connection of unused pins example connection of unused pins
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer usage precaution 128 precautionary notes in using the device a-d converter (1) only write to each bit (except bit 6) of the ad control register 0, or each bit of the ad control register 1, or bit 0 of the ad control register 2 when ad conversion is stopped (before a trigger occurs). when the vref connection bit is changed from 0 to 1, wait 1 s or longer before starting ad conversion. (2) when changing ad operation mode, select an analog pin again. (3) one shot mode read the ad register only after confirming ad conversion is completed, which can be determined by using the ad conversion interrupt. (4) repeat mode use the undivided main clock as the internal cpu clock when using this mode. the main clock can be divided by an internal divider circuit but make sure that you use main clock when using this mode. (5) if a-d conversion is forcibly terminated while in progress by setting the adst bit of adcon0 register to 0 (a- d conversion halted), the conversion result of the a-d converter is indeterminate. if the adst bit is cleared to 0 in a program, ignore the value of ad register. stop and wait mode (1) you must put at least four nops after a stop (all-clock stop bit to "1") or a wait instruction. when switching to a stop or wait mode, 4 instructions are prefetched after the stop or wait instruction. and so, ensure that at least four nops follow the stop or wait instruction. serial i/o (1) when reading data from the uarti receive buffer in the clock asynchronous serial i/o mode, data should be read high-byte first then low-byte using byte-size. if data is read as low-byte then high-byte or in word-size, the framing error and parity error flags are cleared. a code example is shown below. mov.b 00a7h. r0h ; read the high-byte of uart0 receive buffer register mov.b 00a6h. r0l ; read the low-byte of uart0 receive buffer register (2) when writing data to the uarti transmit buffer register in the clock asynchronous serial i/o mode with 9-bit transfer data length, data should be written high-byte first then low-byte using byte-size. a code example is shown below. mov.b #xxh, 00a3h ; write the high-byte of uart0 transmit buffer register mov.b #xxh, 00a2h ; write the low-byte of uart0 transmit buffer register
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer usage precaution 129 stop mode (1) after returning from stop mode, an unexpected operation may occur (for example, undefined instruction interrupt, brk instruction interrupt, etc.). execute a jmp.b instruction after an instruction to write data to the all clock stop control bit. a program example is described as follows: mov.b:s #21h, cm1 ; writing to the all clock stop control bit to 1(stop mode) jmp.b l1 l1 : nop nop nop nop interrupts (1) reading address 0 by firmware ? please do not read address 0 by firmware. in the cpu's interrupt processing sequence, when a maskable interrupt occurs, the interrupt information (interrupt no. and interrupt request level) are read from address 0. this read in turn, clears the interrupt request bit to "0" even pending with higher request level. reading address 0 by firmware may cause interrupt cancellation or unexpected interrupts so please do not read address 0 by firmware. (2) stack pointer ? set the value of the stack pointer before accepting interrupts. immediately after a reset, the value of the stack pointer is 0000 16 . accepting an interrupt before setting a value of the stack pointer may produce unpredictable results (runaway program, etc.) make sure that you set the value of the stack pointer before accepting interrupts. (3) external interrupts ? clear the interrupt request bit to "0" when the int0 - int3 polarity is changed. the reason being is that an interrupt request may be generated when the polarity is changed. (4) rewriting the interrupt control register ? when rewriting the interrupt control register, do it at a point where it does not generate an interrupt request for that register. if there is a possibility that an interrupt may occur, disable the interrupt before rewriting. examples are shown below. example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear t1ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer usage precaution 130 example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear t1ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear t1ic int. priority level and int. request bit. popc flg ; enable interrupts. note: the reason why two nop instructions or dummy read were inserted before the fset i for ex. 1 & 2 is to prevent interrupt enable flag from being set, due to the effects of instruction queue, before the rewritten value of the interrupt control register takes effect. ? when an instruction to rewrite the interrupt control register is executed while the interrupt is disabled, depending on the instruction used for rewriting, there are times the interrupt request bit is not set even if an interrupt request for that register has been generated. if this creates a problem, please use any of the instructions below to rewrite the register. instructions : and, or, bclr, bset ? changing the interrupt request bit when attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : mov noise (1) bypass capacitor between v cc and v ss pins ? insert a bypass capacitor (at least 0.1 f) between v cc and v ss pins as noise and latch-up counter- measures. in addition, make sure that connecting lines are the shortest and widest possible. (2) port control registers data read error ? during severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may changed. as a firmware countermeasure, it is recommended to peri- odically re-set the port registers, port direction registers and pull-up control registers. however, you should fully examine before introducing the re-set routine as conflicts may be created between this re- set routine and interrupt routines (i. e. ports are switched during interrupts). (3) cnvss pin wiring ? in order to improve the pin tolerance to noise, insert a pull down resistance (about 5 k ?) between cnvss and vss, and placed as close as possible to the cnvss pin.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer usage precaution 131 timer 1 (1) even if the prescaler 1 and timer 1 are read out simultaneously in word-size, these registers are read byte- by-byte in the microcomputer. consequently, the timer value may be updated during the period these two registers are being read. timers x, y and z (1) these timers stop counting after reset. therefore, set values to timer (x, y, z) and prescaler (x, y, z) before starting counting. (2) even if prescaler (x, y, z) and timer (x, y, z) are read out simultaneously in word-size, these registers are read byte-by-byte in the microcomputer. consequently, the timer value may be updated during the period these two registers are being read. timer x (1) using in the timer x pulse period measurement mode, the effectaul edge rception flag and the timer x under flow flag are setted to "0" by writing a "0" in a program. writing a "1" has no effect. write "1" in the other flag by using the mov instruction when you make the flag of either one side "0" by program. (the clearance of the flag which isn't intend can be prevnted.) example: mov.b #10xxxxxxb,008bh (2) when changing to the timer x pulse period measurement mode from other mode, the contents of the effectaul edge rception flag and the timer x under flow flag are indetermind. write "0" in the effectaul edge rception flag and the timer x under flow flag before starting the timer. timer y (1) when count is stopped by writing "0" to the timer y count start flag, the timer reloads the value of reload register and stops. therefore, the timer count value should be read out before the timer stops. (2) when count is stopped by writing "0" to the timer y count start flag, the timer y interrupt request flag be- comes "1" and an interrupt may occur. thus, disable interrupts before the timer stops. furthermore, set the timer y interrupt request flag to "0" before starting the timer again. timer z (1) when count is stopped by writing "0" to the timer z count start flag, the timer reloads the value of reload register and stops. therefore, the timer count value should be read out before the timer stops. (2) when count is stopped by writing "0" to the timer z count start flag (all modes) or by writing "0" to the one- shot start bit (programmable one-shot generation mode/programmable wait one-shot generation mode), the timer z interrupt request flag becomes "1" and an interrupt may occur. thus, disable interrupts before the timer stops. furthermore, set the timer z interrupt request flag to "0" before starting the timer again.
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer usage precaution 132 timer c (1) when reading out the timer c or timer measurement register, use a word-size instruction. even if the timer c is read out in word-size, the timer value is not updated during the period the high-byte and low-byte are being read. example: mov.w 0091h,r0 ; read out timer c
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 133 table 1.19.1. absolute maximum ratings note 1: extended operating temperature version: -40 to 85 c. when flash memory version is program/erase mode: 25 5 c. specify a product of -40 to 85 c to use it. note 2: extended operating temperature version: -65 to 150 c. note 3: for m30100 (32-pin version), p2 0 , p2 1 , p3 4 to p3 6 , p4 0 to p4 4 , p4 6 and p4 7 are not accessed to external pins. v o - 0.3 to vcc + 0.3 p d ta = 25 ? - 0.3 to 6.5 v ? vcc t stg t opr ? mw v - 40 to 150 (note 2) 300 - 20 to 85 (note 1) p4 0 to p4 7 ,x out p0 0 to p0 7 , p1 0 to p1 7, p2 0, p2 1 , p30 to p3 7 , parameter unit rated value condition symbol operating ambient temperature reset, v ref , x in - 0.3 to vcc + 0.3 v v i p3 0 to p3 7 , p4 0 to p4 7, cnvss p0 0 to p0 7 , p1 0 to p1 7, p2 0, p2 1 , input voltage supply voltage output voltage power dissipation storage temperature iv cc - 0.3 to 3.6v v electrical characteristics
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 134 2.7 5.5 vcc 5.0 v0 vss 0.8vcc v v vcc 0.2vcc 0 - 10.0 5.0 f (x in ) mhz ma 16 f (xc in ) khz5032.768 v v cc =4.2v to 5.5v 7.33 x v cc mhz v ih v il i oh (peak) ma p0 0 to p0 7 , p1 0 to p1 7 , p2 0 , p2 1 , p3 0 to p3 7 , p4 0 to p4 7 , p0 0 to p0 7 , p1 0 to p1 7, p2 0 , p2 1 , p3 0 to p3 7 , p4 0 to p4 7 , i ol (avg) p1 0 to p1 7 10.0 ma x in , reset, cnv ss , high power low power 5.0 0 0 v cc =2.7v to 4.2v - 14.791 typ. max. unit parametersymbol min standard supply voltage supply voltage low input voltage high input voltage - 5.0 i oh (avg) ma high average output current high peak output current 10.0 ma p0 0 to p0 7 , p2 0 , p2 1 , p3 0 to p3 7 , p4 0 to p4 7 , low peak output current main clock input oscillation frequency low average output current subclock oscillation frequency i ol (peak) p1 0 to p1 7 ma 20.0 10.0 high power low power x in , reset, cnv ss , p0 0 to p0 7 , p1 0 to p1 7, p2 0 , p2 1 , p3 0 to p3 7 , p4 0 to p4 7 , p0 0 to p0 7 , p1 0 to p1 7, p2 0 , p2 1 , p3 0 to p3 7 , p4 0 to p4 7 , p0 0 to p0 7 , p2 0 , p2 1 , p3 0 to p3 7 , p4 0 to p4 7 , (note 5) (note 1) i ol (avg) i ol (peak) note 1: for applications for automobile use, this value is 4.2v. note 2: unless otherwise noted: v cc = 2.7v to 5.5v, ta = 20 to 85 o c note 3: the average output current is an average value measured over 100ms. note 4: keep output current as follows: the sum of port p0 0 to p0 3 , p1 3 to p1 7 , p2 0 , p3 4 to p3 7 , p4 6 to p4 7 i ol (peak) is under 60 ma. the sum of port p0 0 to p0 3 , p1 3 to p1 7 , p2 0 , p3 4 to p3 7 , p4 6 to p4 7 i oh (peak) is under 60 ma. the sum of port p0 4 to p0 7 , p1 0 to p1 2 , p2 1 , p3 0 to p3 3 , p4 0 to p4 5 i ol (peak) is under 60 ma. the sum of port p0 4 to p0 7 , p1 0 to p1 2 , p2 1 , p3 0 to p3 3 , p4 0 to p4 5 i oh (peak) is under 60 ma. note 5: relationship between main clock oscillation frequency and supply voltage is shown as below. note 6: for m30100 (32-pin version), p2 0 , p2 1 , p3 4 to p3 6 , p4 0 to p4 4 , p4 6 and p4 7 are not accessed to external pins. table 1.19.2. recommended operating conditions (note 1) aaa aaa aaa 5.54.22.7 0.0 5.0 16.0 main clock input oscillation frequency power supply voltage [v] ( m a in c l oc k : n o d ivi s i o n ) highest operation frequency [mhz] 7.33 x vcc - 14.791mhz
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 135 v oh v 4.7 3.0 i oh = - 5 ma i oh = - 200 a p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 v v oh x out v 3.0 3.0 i oh = - 1 ma i oh = - 0.5 ma symbol standard typ. unit measuring condition min. max. parameter high output voltage high output voltage v oh x cout v 3.3 3.0 no load no load high output voltage high power low power high power low power v ol v 2.0 i ol = 5 ma i ol = 200 a 0.45 v low output voltage i ih v ram v t+ -v t- v t+ -v t- 0.2 0.8 v 0.2 1.8 v 5.0 a a when clock is stopped 2.0 v 1200 reset cntr 0 ,tcin, int 0 to int 3 ,clk 0 ,clk 1 v i = 5v v i = 0v -5.0 300 i il v ol x out v 2.0 2.0 i oh = 1 ma i oh = 0.5 ma k ? 167.0 50.030.0 hysteresis hysteresis high input current low input current ram retention voltage oscillation frequency of ring oscillator low output voltage v ol xc out high power low power high power low power v 0 0 low output voltage v i = 0v r pullup pull-up resistor m ? 1.0 r f xin x in feedback resistor m ? 6.0 r f xcin x cin feedback resistor khz no load no load reset, cnvss rxd 0 , rxd 1 ,ki 0 to ki 3 ,p4 5 p0 0 to p0 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 , x in reset, cnvss p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 , x in p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 mask rom flash memory 600 3.3 1.6 no load no load flash memory mask rom flash memory mask rom r osc note: the v oh standard values of x cout differ between flash memory version and mask rom version. therefore, please note that the oscillation constants of sub clock may differ between these versions. (note) 1200 300 600 v ol v 2.0 2.0 i oh = 10 ma i oh = 5 ma low output voltage high power low power p1 0 to p1 7 (unless otherwise noted: v cc = 5v, v ss = 0v at ta = 25 o c, f(x in ) = 16mhz) v cc = 5v table 1.19.3. (1) electrical characteristics
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 136 symbol standard typ. unit measuring condition min. max. parameter icc ma 20.0 36.0 power supply current f(x in )=16mhz square wave, no division i/o pin has no load mask rom 100 400 800 ring oscillator mode no division ring oscillator mode when a wait instruction is executed mask rom flash memory ring oscillator mode no division mask rom 1300 a 700 a 50 f(x cin )=32khz square wave f(x cin )=32khz when a wait instruction is executed 2 20 ta=25 c when clock is stopped ta=85 c when clock is stopped a mask rom flash memory f(x cin )=32khz square wave mask rom a 6 flash memory ring oscillator mode when a wait instruction is executed a f(x cin )=32khz when a wait instruction is executed flash memory 350 600 600 ta=25 c when clock is stopped ta=85 c when clock is stopped a mask rom flash memory ma 18.0 36.0 f(x in )=16mhz square wave, no division flash memory a a a a 300 300 (unless otherwise noted: v cc = 5v, v ss = 0v at ta = 25 o c, f(x in ) = 16mhz)) v cc = 5v table 1.19.3. (2) electrical characteristics
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 137 v cc = 5v C C bits lsb v ref =v cc 3 10 v ref =v cc = 5v r ladder t conv k ? s v v ia v ref v 0 2 10 v cc v ref 40 3.3 s 2.8 t conv t samp 0.3 s v ref =v cc v ref =v cc = 5v lsb 3 v ref = v cc = 5v 2 lsb symbol standard typ. unit measuring condition min. max. parameter resolution absolute accuracy ladder resistance conversion time(10bit) reference voltage analog input voltage conversion time(8bit) sampling time sample & hold function not available sample & hold function available(10bit) sample & hold function available(8bit) 7 an 0 to an 11 input anex 0 , anex 1 input, external op-amp connected mode f(x in )=10mhz, ? ad =f ad =10mhz f(x in )=10mhz, ? ad =f ad =10mhz f(x in )=10mhz, ? ad =f ad =10mhz f(x in )=10mhz, ? ad =f ad =10mhz f(x in )=10mhz, ? ad =f ad =10mhz lsb note 1: unless otherwise noted: v cc = v ref =5v, v ss = 0v at ta = 25 o c, f(x in ) = 16mhz note 2: divide the f ad if f(x in ) exceeds 10mhz, and make ad operation clock frequency (? ad ) equal to or lower than 10mhz. min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % k ? ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20104 s (note 2) standard note 1: unless otherwise noted: v cc = v ref =5v, v ss = 0v at ta = 25 o c, f(x in ) = 16mhz note 2: the a-d converter's ladder resistance is not included. when d-a register contents are not "00 16 ", the current i vref always flows even though v ref may have been set to be unconnected by the a-d control register. table 1.19.4. a-d conversion characteristics (note 1) table 1.19.5. d-a conversion characteristics (note 1)
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 138 v cc = 5v cntr0 input low pulse width cntr0 input high pulse width parametersymbol cntr0 input cycle time standard unit min. max. ns t wl(cntr0) ns ns t wh(cntr0) t c(cntr0) 40 100 40 symbol parameter standard unit min. max. tcin input low pulse width tcin input high pulse width tcin input cycle time note1 : use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value. note2 : use the g reater value,either ( 1/ di g ital filter clock fre q uenc y x 3 ) or min. value. 400 (note1) 200 (note2) 200 (note2) ns ns ns t c(tcin) t wh(tcin) t wl(tcin) symbol parameter standard unit min. max. x in input low pulse width x in input high pulse width x in input cycle time 62.5 30 30 ns ns ns t c(x in ) t wh(x in ) t wl(x in ) ns ns t w(inh) t w(inl) ns ns ns ns ns ns ns t c(ck) t w(ckh) t w(ckl) t d(c-q) t su(d-c) t h(c-q) t h(c-d) parametersymbol standard unit min. max. parametersymbol standard unit min. max. clki input cycle time clki input high pulse width clki input low pulse width txdi hold time rxdi input setup time txdi output delay time rxdi input hold time inti input low pulse width inti input high pulse width 250 (note1) 250 (note2) 200 100 100 0 30 90 80 note1 : when the int0 input filter select bit selects the digital filter, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. note2 : when the int0 input filter select bit selects the digital filter, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. timing requirements (unless otherwise noted: v cc = 5v, v ss = 0v at ta = 25 o c) table 1.19.8. tcin input table 1.19.6. x in input table 1.19.9. serial i/o _______ table 1.19.10. external interrupt inti input table 1.19.7. cntr0 input
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 139 p0 p1 p2 p3 p4 30pf figure 1.19.1. port p0 to p4 measurement circuit figure 1.19.2. vcc=5v timing diagram
electrical characteristics (vcc = 5v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 140 cntr0 input tcin input t c(cntr0) t wh(cntr0) t wl(cntr0) t c(tcin) t wh(tcin) t wl(tcin) t su(d-c) clk i txd i rxd i t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) x in input t c(xin) t wh(xin) t wl(xin) v cc = 5v
electrical characteristics (vcc = 3v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 141 v oh v 2.5 i oh = - 1 ma p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 v oh x out v 2.5 2.5 i oh = - 0.1 ma i oh = - 50 a symbol standard typ. unit measuring condition min. max. parameter high output voltage high output voltage v oh x cout v vcc 3.0 no load no load high output voltage high power low power high power low power v ol v 0.5 i ol = 1 ma low output voltage i ih v ram v t+ -v t- v t+ -v t- 0.2 0.8 v 0.2 1.8 v 4.0 ? ? when clock is stopped 2.0 v reset cntr 0 ,tc in , int 0 to int 3 ,clk 0 ,clk 1 v i = 3v v i = 0v -4.0 i il v ol x out v 0.5 0.5 i oh = 0.1 ma i oh = 50 a k ? 500.0120.0 66.0 hysteresis hysteresis high input current low input current ram retention voltage low output voltage v ol xc out high power low power high power low power v 0 0 low output voltage v i = 0v r pullup pull-up resistor m ? 3.0 r f xin x in feedback resistor m ? 10.0 r f xcin x cin feedback resistor no load no load reset, cnvss rxd 0 , rxd 1 ,ki 0 to ki 3 ,p4 5 p0 0 to p0 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 , x in reset, cnvss p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 , x in p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 ,p2 1 , p3 0 to p3 7 ,p4 0 to p4 7 vcc 1.6 no load no load flash memory mask rom flash memory mask rom 600 150 oscillation frequency of ring oscillator khz mask rom flash memory 300 r osc 1000 250 500 note: the v oh standard values of x cout differ between flash memory version and mask rom version. therefore, please note that the oscillation constants of sub clock may differ between these versions. (note) v ol p1 0 to p1 7 v 0.5 0.5 i oh = 2 ma i oh = 1ma low output voltage high power low power (note: unless otherwise noted: v cc = 3v, v ss = 0v at ta = 25 o c, f(x in ) = 5mhz) v cc = 3v table 1.19.11. (1) electrical characteristics
electrical characteristics (vcc = 3v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 142 symbol standard typ. unit measuring condition min. max. parameter icc ma 4.0 8.0 power supply current f(x in )=5mhz square wave, no division i/o pin has no load mask rom 40 350 200 ring oscillator mode no division ring oscillator mode when a wait instruction is executed mask rom flash memory ring oscillator mode no division mask rom 1000 ? 550 ? 30 f(x cin )=32khz square wave f(x cin )=32khz when a wait instruction is executed 2 20 ta=25 c when clock is stopped ta=85 c when clock is stopped ? mask rom flash memory f(x cin )=32khz square wave mask rom ? 4 flash memory ring oscillator mode when a wait instruction is executed ? f(x cin )=32khz when a wait instruction is executed flash memory 300 500 500 ta=25 c when clock is stopped ta=85 c when clock is stopped ? mask rom flash memory ma 8.0 14.0 flash memory ? ? ? ? 250 250 f(x in )=5mhz square wave, no division (unless otherwise noted: v cc = 3v, v ss = 0v at ta = 25 o c, f(x in ) = 5mhz) v cc = 3v table 1.19.11. (2) electrical characteristics
electrical characteristics (vcc = 3v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 143 v cc = 3v bits lsb v ref =v cc ? 10 v ref =v cc = 3v, ad =f ad /2 r ladder k ? v v ia v ref v 0 2.7 10 v cc v ref 40 s 14.0 t conv v ref =v cc symbol standard typ. unit measuring condition min. max. parameter resolution absolute accuracy ladder resistance reference voltage analog input voltage conversion time(8-bit) sample & hold function not available (8-bit) note: unless otherwise noted: v cc = v ref =3v, v ss = 0v at ta = 25 o c, f(x in ) = 7mhz min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % k ? ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20104 s (note 2) standard note 1: unless otherwise noted: v cc = av cc =v ref = 3v, v ss = av ss =0v at ta = 25 o c, f(x in ) = 7mhz note 2: the a-d converter's ladder resistance is not included. when d-a register contents are not "00 16 ", the current i vref always flows even though v ref may have been set to be unconnected by the a-d control register. table 1.19.12. a-d conversion characteristics (note) table 1.19.13. d-a conversion characteristics (note 1)
electrical characteristics (vcc = 3v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 144 v cc = 3v cntr0 input low pulse width cntr0 input high pulse width parametersymbol cntr0 input cycle time standard unit min. max. ns t wl(cntr0) ns ns t wh(cntr0) t c(cntr0) 120 300 120 symbol parameter standard unit min. max. tcin input low pulse width tcin input high pulse width tcin input cycle time ns ns ns t c(tc in ) t wh(tc in ) t wl(tc in ) 1200 (note1) 600 (note2) 600 (note2) symbol parameter standard unit min. max. x in input low pulse width x in input high pulse width x in input cycle time ns ns ns t c(x in ) t wh(x in ) t wl(x in ) 143 70 70 note1 : use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value. note2 : use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. ns ns t w(inh) t w(inl) ns ns ns ns ns ns ns t c(ck) t w(ckh) t w(ckl) t d(c-q) t su(d-c) t h(c-q) t h(c-d) parametersymbol standard unit min. max. parametersymbol standard unit min. max. clki input cycle time clki input high pulse width clki input low pulse width txdi hold time rxdi input setup time txdi output delay time rxdi input hold time inti input low pulse width inti input high pulse width 380 (note1) 380 (note2) 300 150 150 0 50 90 160 note1 : when the int0 input filter select bit selects the digital filter, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. note2 : when the int0 input filter select bit selects the digital filter, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. timing requirements (unless otherwise noted: v cc = 3v, v ss = 0v at ta = 25 o c) table 1.19.16. tcin input table 1.19.14. x in input table 1.19.17. serial i/o _______ table 1.19.18. external interrupt inti input table 1.19.15. cntr0 input
electrical characteristics (vcc = 3v) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 145 cntr0 input tcin input t c(cntr0) t wh(cntr0) t wl(cntr0) t c(tcin) t wh(tcin) t wl(tcin) t su(d-c) clk i txd i rxd i t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) x in input t c(xin) t wh(xin) t wl(xin) v cc = 3v figure 1.19.3. vcc=3v timing diagram
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 146 table 1.20.1. outline performance of the m16c/10 (flash memory version) outline performance table 1.20.1 shows the outline performance of the m16c/10 (flash memory version). item program/erase voltage performance flash memory operation mode standard serial i/o program method collective program erase method collective erase vcc=5.0v10% program/erase count 100 times note: the boot rom area contains a control program which is used to communicate with a dedicated external device (writer). this area cannot be erased nor programmed. erase block division one division (24 kbytes) one division (384 bytes) (note) user rom area boot rom area data retention 10 years power supply voltage 4.2v to 5.5v when f(x in )=16mhz
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 147 flash memory the m16c/10 (flash memory version) contains the flash memory that can be rewritten with a single volt- age. for this flash memory, one mode is available in which to read, program, and erase: standard serial i/ o mode in which the flash memory can be manipulated using a decicated external device (writer). figure 1.20.1 shows the on-chip flash memory. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control communications with the dedicated external device (writer) in the standard serial i/o mode. this boot rom area cannot be erased nor rewritten. figure 1.20.1. block diagram of flash memory version 0fa000 16 user rom area (24kbytes) 0ffe80 16 0fffff 16 0fffff 16 boot rom area (384bytes) note : the boot rom area cannot be erased / written. flash memory size flash memory start address 24kbytes 0fa000 16 type m30100f3 M30102f3
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 148 pin description v cc ,v ss apply program/erase protection voltage (5v10%) to vcc pin and 0 v to vss pin. cnv ss connect to vcc. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to x in pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out v ref enter the reference voltage for ad from this pin. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p2 0 to p2 7 input "h" or "l" level signal or open. p3 0 to p3 7 input "h" or "l" level signal or open. p4 0 to p4 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 i/o i i i o i i i i i i iv cc connect a capacitor (0.1 f) to vss pin. iv cc pin functions (flash memory standard serial i/o mode)
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 149 figure 1.20.2. pin connections for serial i/o mode (1) 12345 6 78 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 29 28 27 26 25 32 31 30 cnvss vcc vss to vcc reset signal value mode setup method * vcc = 5v 10% clk0 rxd0 txd0 v ss v cc busy reset connect oscillator circuit. 0.1 f x in x out v ss reset v cc cnv ss p1 7 /cntr 0 p1 6 /clk 0 p1 5 /rxd 0 p1 4 /txd 0 p0 3 /an 4 p0 2 /an 5 p0 1 /an 6 p0 0 /an 7 p3 7 /txd 1 /rxd 1 p0 7 /an 0 p3 3 /tcin p3 0 /tx out p3 2 /ty out p3 1 /tz out ivcc v ss v cc p0 6 /an 1 p0 5 /an 2 p0 4 /an 3 v ref p4 5 /int 0 m30100f3fp m30100f3tfp p1 0 /ki 0 /an 8 p1 1 /ki 1 /an 9 p1 2 /ki 2 /an 10 p1 3 /ki 3 /an 11 package: 32p6u-a
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 150 figure 1.20.3. pin connections for serial i/o mode (2) 12345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 2536 35 34 33 45 44 43 42 41 48 47 46 40 39 38 37 cnvss vcc vss to vcc reset signal value mode setup method * vcc = 5v 10% M30102f3fp M30102f3tfp x in x out v ss reset v cc cnv ss p4 6 /x cout p4 7 /x cin p1 7 /cntr 0 p1 6 /clk 0 p1 5 /rxd 0 p1 4 /txd 0 p0 3 /an 4 p0 2 /an 5 p0 1 /an 6 p0 0 /an 7 p3 7 /txd 1 /rxd 1 p3 6 /clk 1 p3 5 /rxd 1 p3 4 /clks 1 /da p0 7 /an 0 p4 1 /anex 1 p3 0 /tx out p4 0 /anex 0 p3 1 /tz out p3 2 /ty out ivcc p3 3 /tcin v ss v cc p0 6 /an 1 p0 5 /an 2 p0 4 /an 3 v ref p4 2 /int 3 p4 3 /int 1 p2 1 n.c p2 0 n.c n.c n.c busy clk0 rxd0 txd0 v ss reset connect oscillator circuit. v cc 0.1 f p4 5 /int 0 p4 4 /int 2 p1 0 /ki 0 /an 8 p1 1 /ki 1 /an 9 p1 2 /ki 2 /an 10 p1 3 /ki 3 /an 11 package: 48p6q-a
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 151 standard serial i/o mode the standard serial i/o mode inputs and outputs the control functions, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. this i/o is serial. there are actually two standard serial i/o modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. both modes require a dedicated external device (writer). in the standard serial i/o mode, the cpu controls rewrite to the flash memory and communication with the dedicated external device (writer). this mode starts when the reset is released, which is done when the cnvss pin is "h" level. (in the ordinary microprocessor mode, set cnvss pin to "l" level.) this control program for communications with the dedicated external device (writer) is written in the boot rom area when the product is shipped from mitsubishi. accordingly, make note of the fact that the boot rom area cannot be erased nor rewritten. figures 1.20.2 and 1.20.3 show the pin connections for the standard serial i/o mode. the communications with the dedicated external device (writer) uses uart0. standard serial i/o switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of clk 0 pin when the reset is released. to use standard serial i/o mode 1 (clock synchronized), set the clk 0 pin to "h" level and release the reset. the operation uses the four uart0 pins clk 0 , rxd 0 , txd 0 and busy. to use standard serial i/o mode 2 (clock asynchronized), set the clk 0 pin to "l" level and release the reset. the operation uses the two uart0 pins rxd 0 and txd 0 . the busy pin should be open.
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 152 example circuit application for the standard serial i/o mode 1 the below figure shows a circuit application for the standard serial i/o mode 1. control pins will vary according to dedicated external device (writer), therefore see the dedicated external device (writer) manual for more information. figure 1.20.4. example circuit application for the standard serial i/o mode 1 busy clk0 r x d0 t x d0 cnvss clock input busy output data input data output (1) control pins and external circuitry will vary according to the dedicated external device (writer). for more information, see the dedicated external device (writer) manual. (2) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. m16c/10 group (flash memory version)
appendix standard serial i/o mode (flash memory version) under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 153 example circuit application for the standard serial i/o mode 2 the below figure shows a circuit application for the standard serial i/o mode 2. figure 1.20.5. example circuit application for the standard serial i/o mode 2 busy clk0 r x d0 t x d0 cnvss monitor output data input data output (1) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. m16c/10 group (flash memory version)
under development tentative specifications rev.e1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30100/M30102 group single-chip 16-bit cmos microcomputer 154 package package lqfp32-p-0707-0.80 weight(g) e jedec code eiaj package code lead material cu alloy 32p6u-a plastic 32pin 7 ? 7mm body lqfp e 0.1 e ee 0.2 e e ee e e ee e symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 ee i 2 1.0 ee m d ee m e 10 lqfp48-p-77-0.50 weight(g) jedec code eiaj package code lead material cu alloy 48p6q-a plastic 48pin 7 ? 7mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 7.4 m e 7.4 8 0 0.1 1.0 0.650.50.35 9.29.08.8 9.29.08.8 0.5 7.17.06.9 7.17.06.9 0.1750.1250.105 0.270.220.17 1.4 0 1.7 e e e h e 1 48 37 24 25 36 12 13 h d d m d m e a f y b 2 i 2 recommended mount pad a 1 a 2 l 1 l detail f lp a3 c lp 0.45 0.6 0.25 0.75 0.08 x a3 e b x m mmp
revision history m30100/M30102 group data sheet rev. date description page summary 155 b 04/20/01 figure and table numbers are revised. features are partly revised. page numbers of table of contents are partly revised. figure 1.1.1 to figure 1.1.3 are partly revised. figure 1.1.4 to figure 1.1.6 are partly revised. table 1.1.1 is partly revised. figure 1.1.7 is partly revised. figure 1.1.8 is partly revised. pin description is partly revised. explanation of memory is partly revised. explanation of reset is partly revised. figure 1.5.2 (example reset circuit for voltage check circuit )is added. figure 1.5.3 is partly revised. figure 1.5.4 is partly revised. explanation of software reset is partly revised. processor mode register 0 in figure 1.5.5 is partly revised. note 2 is deleted. processor mode register 1 is added to figure 1.5.5. figure 1.6.1 and figure 1.6.2 are partly revised. table 1.8.1 is partly revised. figure 1.8.1 is partly revised. external rc oscillator is added. figure 1.8.4 is partly revised. figure 1.8.5 is added. explanation of stop mode is partly revised. table 1.8.4 is partly revised. figure 1.9.1 is partly revised. explanation of oscillation stop detection function is partly revised. table 1.10.1 is partly revised. figure 1.10.1 is partly revised. figure 1.10.2 is partly revised. note 2 and note 3 is partly revised. note 5 is deleted. explanation of oscillation stop detection interrupt enable bit (cm21) partly revised. operation select bit (cm27) is deleted. figure 1.11.1 is partly revised. uart1 receive interrupt in (1) special interrupts is partly revised. timer c interrupt in (2) peripheral i/o interrupt is partly revised. table 1.12.2 is partly revised. figure 1.12.3 is partly revised. table 1.12.5 is partly revised. figure 1.12.9 is partly revised. _______ explanation of int interrupt is partly revised. external interrupt enable register in figure 1.12.10 is partly revised. explanation of key interrupt is partly revised. figure 1.12.13 is partly revised. figure 1.12.14 is partly revised. explanation of watchdog timer is partly revised. explanation of timer 1 is partly revised. figure 1.14.2 is partly revised. figure 1.14.3 is partly revised. note 1 and note 2 are added. explanation of (2) pulse output mode is partly revised. explanation of (4) pulse width measure mode is partly revised. all pages 1 1 2 - 4 5 - 7 8 9 9 10 11 15 15 15 16 17 17 17 18 - 19 21 21 24 25 26 27 29 31 31 32 32 33 33 35 38 38 40 42 46 50 51 51 53 53 53 56 58 59 59 60 60
revision history m30100/M30102 group data sheet rev. date description page summary 156 explanation of (5) pulse period measure mode is partly revised. explanation of precaution is partly revised. figure 1.14.4 is partly revised. explanation of timer y is partly revised. explanation of (2) programmable waveform generation mode is partly revised. figure 1.14.5 is partly revised. figure 1.14.6 is partly revised. note 1 and note 2 are added to timer y, z mode register in figure 1.14.6. explanation of timer z is partly revised. figure 1.14.7 is partly revised. figure 1.14.9 is partly revised. explanation of (2) programmable waveform generation mode is partly revised. explanation of timer c is partly revised. figure 1.14.10 is partly revised. note 1 is added to timer c control register 0 in figure 1.14.10. figure 1.14.11 is partly revised. figure 1.14.12 is partly revised. table 1.14.1 and its note are partly revised. figure 1.15.1 is partly revised. note is added to uarti transmit/receive mode register in figure 1.15.4 is partly revised. uarti transmit/receive control register 0 in figure 1.15.4 is partly revised. note 1 and note 2 of uarti transmit/receive control register 0 in figure 1.15.4 are deleted . note 1 is added to uarti transmit/receive control register 1 in figure 1.15.5. uarti transmit/receive control register 2 is added to figure 1.15.5. table 1.15.2 is partly revised. figure 1.15.10 is partly revised. table 1.15.3 is partly revised. table 1.15.4 is partly revised. explanation of a-d converter is partly revised. table 1.16.1 is partly revised. figure 1.16.1 is partly revised. a-d control register 0 in figure 1.16.2 is partly revised. figure 1.16.3 is partly revised. input pin and note in table 1.16.3 are revised. figure 1.16.5 is partly revised. explanation of extended analog input pins is partly revised. explanation of external operation amp connection mode is partly revised. explanation of d-a converter is partly revised. figure 1.17.1 is partly revised. figure 1.17.3 is partly revised. explanation of programmable i/o ports is partly revised. figure 1.18.2 is revised. figure 1.18.3 is revised. figure 1.18.4 is revised. figure 1.18.5 is revised. figure 1.18.6 is revised. table 1.18.1 is revised. 61 61 61 62 63 64 65 65 66 66 67 68 72 72 72 73 73 74 75 78 78 78 79 79 81 84 85 86 89 89 90 91 92 94 94 95 95 96 96 97 98 100 101 102 103 104 105 b1 05/15/01 15 19 31 figure 1.5.3 is partly revised. figure 1.6.2 is partly revised. table 1.10.1 is partly revised.
revision history m30100/M30102 group data sheet rev. date description page summary 157 figure 1.10.1 is partly revised. _______ explanation of int interrupt is partly revised. note 3 is added to table 1.16.1. figure 1.16.2 is partly revised. figure 1.16. 3 is partly revised. table 1.16.2 is partly revised. table 1.16.3 is partly revised. figure 1.16.5 is partly revised. 32 51 89 91 92 93 94 94 features are partly revised. page numbers of table of contents are partly revised. figure 1.1.1 to 1.1.4 are partly revised. table 1.1.1 is partly revised explanation of (3) package if partly revised. figure 1.1.7 is partly revised. pin description is partly revised. figure 1.3.1 is partly revised. explanation of reset is partly revised. figure 1.5.3 is partly revised. figure 1.5.4 is partly revised. figure 1.6.2 is partly revised. figure 1.8.1 is partly revised. explanation is partly revised. figure 1.8.3 is partly revised. explanation of (1)main clock, (3)bclk and (7)f ring are partly revised. note (2) and (5) of register cm1 in figure 1.8.4 are partly revised. register cm2 in figure 1.8.5 is partly revised. explanation of stop mode is partly revised. explanation of status transition of bclk, (3)division by 8 mode, (5)no-division mode and (8)ring oscillation mode are partly revised. note is added. explanation of power control is partly revised. figure 1.9.2 is partly revised. explanation of oscillation stop detection function is partly revised. table 1.10.1 is partly revised. figure 1.10.1 and 1.10.2 are partly revised. explanation of cm20 to cm22 are partly revised. explanation of protection is partly revised. explanation of uart1 receive interrupt of (1)special interrupts is partly revised. _______ _______ explanation of int0 to int3 interrupt of (2)peripheral i/o interrupts is partly revised. table 1.12.2 is partly revised. program examples are partly revised. _______ explanation of int interrupt is partly revised. figure 1.12.10 is partly revised. figure 1.12.11 is partly revised. explanation of key input interrupt is partly revised. figure 1.12.13 and 1.12.14 is partly revised. explanation of (1)reading address 00000 16 is partly revised. latch used for reload register related are changed to reload register. expression of counter content is changed from 00h to 00 16 . 01 01 02 - 05 08 09 09 10 11 15 15 16 19 21 22 22 23 24 25 26 27 27 29 31 32 32 33 34 36 39 39 41 45 52 52 53 54 54 56 59 - 72 59 - 72 c1 11/20/01
revision history m30100/M30102 group data sheet rev. date description page summary 158 figure 1.14.3 is partly revised. explanation of (3) event counter mode is partly revised. explanation of (4) pulse width measure mode is partly revised. explanation of (5) pulse period measure mode is partly revised. figure 1.14.4 is partly revised. explanation of (2) programmable waveform generation mode is partly revised. explanation of use of the waveform extend function is added. last paragraph in precaution is partly revised. figure 1.14.6 is partly revised. figure 1.14.7 is partly revised. figure 1.14.8 and 1.14.9 are partly revised. explanation of (2) programmable waveform generation mode is partly revised. explanation of (3) programmable one-shot generation mode is partly revised. explanation of (4) programmable wait one-shot generation mode is partly revised. explanation of use of the waveform extend function is added. explanation of change of set count values is partly revised. last paragraph in precaution is partly revised. figure 1.14.10 is partly revised. figure 1.15.1 is partly revised. figure 1.15.2 is partly revised. figure 1.15.3 is partly revised. figure 1.15.4 is partly revised. figure 1.15.5 is partly revised. table 1.15.1 is partly revised. figure 1.15.7 is partly revised. (e) rxd 1 input pin selection function (uart) is added. table 1.15.3 is partly revised. figure 1.15.13 is partly revised. (b) rxd 1 input pin selection function (uart) is added. table 1.16.1, note 2 is partly revised. figure 1.16.1 is partly revised. figure 1.16.2 is partly revised. figure 1.16.4 is partly revised table 1.16.3 is partly revised. figure 1.16.5 is partly revised explanation of extended analog input pins is partly revised. figure 1.16.6 is partly revised. explanation of programmable i/o ports is partly revised. figure 1.18.1 to 1.18.6 are partly revised. table 1.18.1 is partly revised. explanation of usage of precaution is added. section of electric characteristics is added. 60 61 61 62 62 64 65 65 66 67 68 69 70 71 72 72 72 73 76 77 78 79 80 81 83 85 86 89 89 90 91 92 94 95 95 96 96 99 100 - 105 106 107 - 108 109 - 119 1 3(ver.c) 6(ver.c) 6 7 7 8 9 d july/08/02 explanation of overview is partly revised. figure 1.1.2 is deleted. figure 1.1.5 is deleted. table 1.1.1 is partly revised. (3)package is partly revised. figures 1.1.7 and 1.1.8 are partly revised. explanation on cnvss of pin description is partly revised. explanation of operation of functional blocks is partly revised.
revision history m30100/M30102 group data sheet rev. date description page summary 159 9 9 14 18 19 20 21 21 23 23 30 31 35 37 37 38 49 49 51 51 53(rev.c) 52 53 57 58 59-94 97 98 99 99 100 101 102 104 105 106 108 113 114 118 119-122 123 124 126 127 129 129 130 131 explanation of memory is partly revised. figure 1.3.1 is partly revised. figure 1.5.4 is partly revised. figure 1.7.1 is partly revised. table 1.8.1 is partly revised. figure 1.8.3 is partly revised. explanation of (1) main clock is partly revised. explanation of (5) fc 32 is partly revised. figure 1.8.5 is partly revised. figure 1.8.6 is added. explanation of oscillation stop detection function is partly revised. figure 1.10.2 is partly revised. figure 1.12.1 is partly revised. explanation of uart0 receive interrupt of (1)special interrupts is partly revised. explanation of cntr0 interrupt and tcin interrupt are added to (2)peripheral i/o interrupts instead of cntr0 and tcin interrupt. table 1.12.1 is partly revised. figure 1.12.8 is partly revised. figure 1.12.9 is partly revised. explanation of int0 input filter is partly revised. figure 1.12.11 is partly revised. explanation of uart0 receive hardware input and figure 1.12.12 are deleted. explanation of cntr0 interrupt and figure 1.12.13 are added. explanation of tcin interrupt and figure 1.12.14 are added. figure 1.13.1 is partly revised. pm1 register is added to figure 1.13.2. timer: full-fledged revision note is added to uarti transmit buffer register in figure 1.15.3. uarti transmit/receive control register 0 of fig 1.15.4 is partly revised. note of uarti transmit/receive control register 1 of fig 1.5.5 is partly revised. note 2 is added to uart transmit/receive control register 2 in fig 1.15.5. table 1.15.1 note 1 is partly revised. table 1.15.2 is partly revised. figure 1.15.7 is partly revised. explanation of (e) is partly revised. note 1 of table 1.15.1 is partly revised. table 1.15.4 is partly revised. explanation of (b) is partly revised. figure 1.16.4 is partly revised. figure 1.16.5 is partly revised. figure numbers are revised. figures 1.18.1 to 1.18.4 are partly revised. figure 1.18.5 is partly revised. figure 1.18.6 is partly revised. note 1 is added to table 1.18.1. (2) is added to explanation of precautionary note of serial i/o. (3) is added to explanation of precautionary note of noise. explanation of precautionary notes of timers y, z and c are added. notes 2 and 3 of table 1.19.2 are partly revised. note 5 of table 1.19.2 is partly revised.
revision history m30100/M30102 group data sheet rev. date description page summary 160 table 1.19.3 (1) and (2) are partly revised. table 1.19.11 (1) and (2) are partly revised. section flash memory version is added. 132-133 138-139 143-150 d1 aug/09/02 explanation of overview is partly revised. power supply voltage in features is partly revised. flash memory version is added to the table of contents. fig 1.1.1 is partly revised fig 1.1.2 is partly revised. table 1.1.6 is partly revised. figs 1.5.1 and 1.5.2 are partly revised. note is added to figs 1.6.1 and 1.6.2. note is added to table 1.8.1. note 2 is added to fig 1.8.1. explanation of ring oscillator is partly revised. fig 1.8.3 is partly revised. explanation of (3)bclk is partly revised. explanation of (4) peripheral function clock is partly revised. note 8 for cm0 and note 1 for cm1 in fig 1.8.4 are partly revised. explanation of stop mode is partly revised. explanation of (5) no-division mode is partly revised. explanation of (3) stop mode is partly revised. explanation of changing the interrupt request bit is added. explanation of changing the interrupt request bit is added. explanation of wdt is partly revised. explanation of timer is partly revised. note is added to table 1.14.1. fig 1.14.1 is partly revised. tcss register in fig 1.14.2 is partly revised. fig 1.14.3 is partly revised. tcss register in fig 1.14.5 is partly revised. table 1.14.7 partly revised. note is added to table 1.14.7. note is deleted from fig 1.14.11. fig 1.14.13 is partly revised. tyzoc register in fig 1.14.15 is partly revised. tcss register in fig 1.14.16 is partly revised. note 1 and note 2 are added to table 1.14.8. explanation of (2) programmable waveform generation mode is partly revised. notes of table 1.14.9 are partly revised. note is added to fig 1.14.19. fig 1.14.20 is partly revised. tcss register in fig 1.14.23 is partly revised. tyzoc register in fig 1.14.24 is partly revised. note 1 and note 2 are added to table 1.14.10. explanation of (2) programmable waveform generation mode is partly revised. notes of table 1.14.11 are partly revised. notes of table 1.14.12 are partly revised. note 3 of pum in fig 1.14.27 is partly revised. fig 1.14.28 is partly revised. 1 1 1 2 3 6 13 16 19 19 20 20 21 21 22 24 25 27 43 56 57 59 59 60 61 62 63 69 69 69 70 71 72 73 75 75 77 78 81 82 83 85 85 87 88 89
revision history m30100/M30102 group data sheet rev. date description page summary 161 explanation of (4) programmable wait one-shot generation mode is partly revised. notes of table 1.14.13 are partly revised. fig 1.14.30 is added. table 1.14.14 are partly revised. tcc0 register in fig 1.14.32 is partly revised. fig 1.14.33 is partly revised. notes of uitb register and uirb register in fig 1.15.3 are partly revised. uimr register in fig 1.15.4 is partly revised. sleep mode is deleted from select function on table 1.15.3. fig 1.15.11 is partly revised. explanation of (a) sleep mode is deleted. note 2 in table 1.16.1 is partly revised. explanation of serial i/o is partly revised. explanation #5 is added to a-d converter. explanation of stop mode is added. explanation of changing the interrupt request bit is added. explanation of timer 1 and timer x, y, z are added. explanation of #2 of timer y is partly revised. explanation of #2 of timer z is partly revised. explanation of #1 of timer c is partly revised. note 1 is added to table 1.19.2. table 1.19.3 (1) and (2) are partly revised. table 1.19.11 (1) and (2) are partly revised. fig 1.20.1 is partly revised. fig 1.20.2 is partly revised. 90 90 92 93 94 95 98 99 106 107 109 110 127 127 128 129 130 130 130 130 132 133-134 139-140 147 148 e dec/20/02 1 2 3 13 19 20 22 25 26 49 50 52 53 54 54 55 57 61 62 63 64 65 66 67 69 table of contents is partly revised. fig 1.1.1 is partly revised. fig 1.1.2 is partly revised. explanation of reset and fig.1.5.1 are partly revised. table1.18.1 is partly revised. fig 1.8.2 and fig 1.8.3. are partly revised. fig 1.8.4 is partly revised. note is partly revised. table 1.8.4 is partly revised. fig 1.12.9 is partly revised. explanation of int interrupt is partly revised. note 2 and note 3 are added to table 1.12.12. fig 1.12.13. is partly revised. header is partly revised. explanation of key input interrupt is partly revised. header is partly revised. explanation of wdt and fig 1.13.1 are partly revised. note 5 is added to table 1.14.2. fig 1.14.4 is partly revised. note 2 and note 3 are added to fig 1.14.4. note 5 is added to table 1.14.5. fig 1.14.6 is partly revised. note 1 is added to fig 1.14.6. fig 1.14.7 is partly revised. note 3 is added to fig 1.14.7. fig 1.14.8 is partly revised. note 1 is added to fig 1.14.8. fig 1.14.9 is partly revised. note 1 is added to fig 1.14.9. table 1.14.7 is partly revised. note is partly revised.
revision history m30100/M30102 group data sheet rev. date description page summary 162 fig 1.14.11.is partly revised. note 1 and note 2 are added to fig 1.14.11. fig 1.14.12 is added. fig 1.14.16 is partly revised. note 5 is added to fig 1.14.16. note 2 is added to fig 1.14.17. fig 1.14.20 is partly revised. note 4 is added to timer y,z waveform output control register in fig 1.14.23. note 5 is added to timer count source setting register in fig 1.14.23. note 2 is partly revised to timer y,z output control register in fig 1.14.24. note is added to external input enable register in fig 1.14.24. note 2 is added to fig 1.14.25. fig 1.14.27 is partly revised. fig 1.14.32 is partly revised. fig 1.15.7 is partly revised. fig 1.15.13 is partly revised. fig 1.16.6 is partly revised. table 1.18.1 is partly revised and note 3 is added. explanation of timer x is added. table 1.19. 3 (1) is partly revised. table 1.19. 3 (2) is partly revised. table 1.19.6, table 1.19.7 and table 1.19.8 is changed to table.1.19.7, table 1.19.8 and table 1.19.6. note 1 and note 2 are added to table 1.19.8. note 1 and note 2 are added to table 1.19.10. table 1.19. 11 (1) is partly revised. table 1.19. 11 (2) is partly revised. table 1.19.14, table 1.19.15 and table 1.19.16 is changed to table.1.19.15, table 1.19.16 and table 1.19.14. note 1 and note 2 are added to table 1.19.16. note 1 and note 2 are added to table 1.19.18. fig 1.20.2 is partly revised. fig 1.20.3 is partly revised. package is added. 69 70 73 75 79 82 82 83 83 85 89 95 104 110 117 127 131 135 136 138 138 138 141 142 144 144 144 149 150 154 e dec/20/02 e1 feb/13/03 6 7 9 29 134 136 142 table 1.1.1 value of power consumption fig 1.1.5 is partly revised. fig 1.3.1 is partly revised. fig 1.9.2 is partly revised. table 1.19.2 iol(peak)/iol(avg) table 1.19.3(2) icc table 1.19.11(2) icc
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